From ce93cd026259b5724a8de4a2d3bb2e87297ce5e4 Mon Sep 17 00:00:00 2001
From: Anghelo Carvajal <angheloalf95@gmail.com>
Date: Fri, 14 Jul 2023 14:44:11 -0400
Subject: Update subrepos (#19)

* git subrepo pull --force tools/asm-processor

subrepo:
  subdir:   "tools/asm-processor"
  merged:   "6dd4d3a"
upstream:
  origin:   "git@github.com:simonlindholm/asm-processor.git"
  branch:   "main"
  commit:   "6dd4d3a"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull lib/ultralib --force

subrepo:
  subdir:   "lib/ultralib"
  merged:   "0417857"
upstream:
  origin:   "git@github.com:decompals/ultralib.git"
  branch:   "main"
  commit:   "0417857"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull tools/asm-differ --force

subrepo:
  subdir:   "tools/asm-differ"
  merged:   "6d3e4c4"
upstream:
  origin:   "git@github.com:simonlindholm/asm-differ.git"
  branch:   "main"
  commit:   "6d3e4c4"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull tools/splat --force

subrepo:
  subdir:   "tools/splat"
  merged:   "406b646"
upstream:
  origin:   "git@github.com:ethteck/splat.git"
  branch:   "master"
  commit:   "406b646"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* Revert "git subrepo pull lib/ultralib --force"

This reverts commit da9fca47be7d8f957b786c02d7bf4b4a48830f4a.

* git subrepo pull tools/splat

subrepo:
  subdir:   "tools/splat"
  merged:   "7869ef2"
upstream:
  origin:   "git@github.com:ethteck/splat.git"
  branch:   "master"
  commit:   "7869ef2"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* Disable asm size directive
---
 tools/asm-processor/asm_processor.py | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'tools/asm-processor/asm_processor.py')

diff --git a/tools/asm-processor/asm_processor.py b/tools/asm-processor/asm_processor.py
index 0d62bc3..23f6102 100644
--- a/tools/asm-processor/asm_processor.py
+++ b/tools/asm-processor/asm_processor.py
@@ -605,11 +605,11 @@ class GlobalAsmBlock:
         line = re.sub(r'^[a-zA-Z0-9_]+:\s*', '', line)
         changed_section = False
         emitting_double = False
-        if line.startswith('glabel ') and self.cur_section == '.text':
+        if (line.startswith('glabel ') or line.startswith('jlabel ')) and self.cur_section == '.text':
             self.text_glabels.append(line.split()[1])
         if not line:
             pass # empty line
-        elif line.startswith('glabel ') or line.startswith('dlabel ') or line.startswith('endlabel ') or (' ' not in line and line.endswith(':')):
+        elif line.startswith('glabel ') or line.startswith('dlabel ') or line.startswith('jlabel ') or line.startswith('endlabel ') or (' ' not in line and line.endswith(':')):
             pass # label
         elif line.startswith('.section') or line in ['.text', '.data', '.rdata', '.rodata', '.bss', '.late_rodata']:
             # section change
@@ -651,17 +651,22 @@ class GlobalAsmBlock:
             emitting_double = True
         elif line.startswith('.space'):
             self.add_sized(int(line.split()[1], 0), real_line)
-        elif line.startswith('.balign') or line.startswith('.align'):
+        elif line.startswith('.balign'):
             align = int(line.split()[1])
             if align != 4:
                 self.fail("only .balign 4 is supported", real_line)
             self.align4()
+        elif line.startswith('.align'):
+            align = int(line.split()[1])
+            if align != 2:
+                self.fail("only .align 2 is supported", real_line)
+            self.align4()
         elif line.startswith('.asci'):
             z = (line.startswith('.asciz') or line.startswith('.asciiz'))
             self.add_sized(self.count_quoted_size(line, z, real_line, output_enc), real_line)
         elif line.startswith('.byte'):
             self.add_sized(len(line.split(',')), real_line)
-        elif line.startswith('.half'):
+        elif line.startswith('.half') or line.startswith('.hword'):
             self.align2()
             self.add_sized(2*len(line.split(',')), real_line)
         elif line.startswith('.'):
-- 
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