dolphin/Source/Core/Common/Arm64Emitter.cpp, branch release-prep-2503a GameCube and Wii emulator Emitters: Define Trivial Getters Inline 2024-07-22T04:35:29+00:00 mitaclaw 140017135+mitaclaw@users.noreply.github.com 2024-07-22T04:35:29+00:00 ffc7bcfbf81e9c6a005ab1139bc74874d8d4ce35 






Arm64FloatEmitter: 64-Bit Assert In ABI_PushRegisters
2024-05-07T20:51:50+00:00

mitaclaw
140017135+mitaclaw@users.noreply.github.com

2024-05-05T21:26:51+00:00

28f8ab9e8a9593fb05ddc93a3022ee8c6e305292












Replace Common::BitCast with std::bit_cast
2024-05-04T01:43:51+00:00

Pokechu22
Pokechu022@gmail.com

2022-08-06T04:10:17+00:00

fbbfea8e8e536800a6a911eb90cecdd1f343f9e3












Arm64Emitter: Fix shadowed variable
2024-04-21T14:20:59+00:00

JosJuice
josjuice@gmail.com

2024-04-21T14:20:59+00:00

de338317834f08590d59df5c27392f109322d29f

A lambda at the end of ARM64XEmitter::ParallelMoves named its parameter
`move`.





A lambda at the end of ARM64XEmitter::ParallelMoves named its parameter
`move`.







Arm64Emitter: Fix incorrect assert category
2024-04-21T14:19:10+00:00

JosJuice
josjuice@gmail.com

2024-04-21T14:19:10+00:00

e140491fa9108f3b456bd108a2f5a707458868da












Arm64Emitter: Don't optimize ADD to MOV for SP
2024-02-06T20:58:07+00:00

JosJuice
josjuice@gmail.com

2024-02-06T20:58:07+00:00

b5c5371848084f6b8738c3be85267c2cd2c9fbc2

Unlike ADD (immediate), MOV (register) treats SP as ZR. Therefore the
ADDI2R optimization that was added in 67791d227c can't optimize ADD to
MOV when exactly one of the registers is SP.

There currently isn't any code in Dolphin that calls ADDI2R with
parameters that would trigger this case.





Unlike ADD (immediate), MOV (register) treats SP as ZR. Therefore the
ADDI2R optimization that was added in 67791d227c can't optimize ADD to
MOV when exactly one of the registers is SP.

There currently isn't any code in Dolphin that calls ADDI2R with
parameters that would trigger this case.







JitArm64: Fix the "do nothing" cases of ANDI2R and friends
2023-12-21T19:51:32+00:00

JosJuice
josjuice@gmail.com

2023-12-21T19:51:32+00:00

d8c78f2a922623aa03875bd496113bc42622e34d

So somehow I forgot that AArch64 uses three-operand encoding...

Fixes a regression from 6303416201 which manifested in various ways,
such as incorrect rendering of the Wind Waker title screen.





So somehow I forgot that AArch64 uses three-operand encoding...

Fixes a regression from 6303416201 which manifested in various ways,
such as incorrect rendering of the Wind Waker title screen.







JitArm64: Improve codegen in ANDI2R and friends
2023-12-17T17:13:32+00:00

JosJuice
josjuice@gmail.com

2023-12-17T16:51:46+00:00

dc60bc5f1ef19fc92b2dd9c92655bf5f282106dd

The codegen for the functions themselves, not for the emitted code.

This seems to save 32 bytes per function. We also get rid of the oddity
we had before where ANDI2R would do masking for 32-bit operations but
the other functions wouldn't.





The codegen for the functions themselves, not for the emitted code.

This seems to save 32 bytes per function. We also get rid of the oddity
we had before where ANDI2R would do masking for 32-bit operations but
the other functions wouldn't.







JitArm64: Optimize additional cases of ANDI2R and friends
2023-12-17T17:13:32+00:00

JosJuice
josjuice@gmail.com

2023-12-17T16:24:13+00:00

a8e1e1ae48d0c03f60c3fc7cd13856b92590efc8

Now we'll never need a scratch register for values that are all zeroes
or all ones.





Now we'll never need a scratch register for values that are all zeroes
or all ones.







JitArm64: Optimize ANDI2R and friends to no-ops when possible
2023-12-17T17:13:30+00:00

JosJuice
josjuice@gmail.com

2023-12-17T16:15:03+00:00

630341620128684cb7965a0245d0e5f51af7ed45

This optimizes rlwnmx with mask == 0xFFFFFFFF.





This optimizes rlwnmx with mask == 0xFFFFFFFF.