diff options
| author | Sintendo <3380580+Sintendo@users.noreply.github.com> | 2025-02-01 17:58:14 +0100 |
|---|---|---|
| committer | Sintendo <3380580+Sintendo@users.noreply.github.com> | 2025-02-02 12:01:08 +0100 |
| commit | 075c35602fd3d03b0f44363f01c44ff9cd81faa6 (patch) | |
| tree | aec83e59e7cbdb8679789538547524eb608d68c2 | |
| parent | 01eed0a7585fbd3031e850ee8f14778e9e46a0e4 (diff) | |
JitArm64_Integer: cmp - Add shifted 12-bit constant
You can encode a shifted 12-bit immediate in an ADD instruction on
ARM64. If the negated constant fits in this range, we can exploit this
to avoid materializing the immediate.
This approach saves an instruction if it does not need to be
materialized in a register afterwards. Otherwise, we just materialize
it later and the total number of instructions stays the same.
Before:
0x52bff01a mov w26, #-0x800000 ; =-8388608
0x93407f1b sxtw x27, w24
0xcb3ac37b sub x27, x27, w26, sxtw
After:
0x93407f1b sxtw x27, w24
0x9160037b add x27, x27, #0x800, lsl #12 ; =0x800000
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 2175f9a219..242ed1eb42 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -668,6 +668,11 @@ void JitArm64::cmp(UGeckoInstruction inst) SXTW(CR, gpr.R(a)); ADD(CR, CR, ~gpr.GetImm(b) + 1); } + else if (gpr.IsImm(b) && (((~gpr.GetImm(b) + 1) & 0xFFF000) == (~gpr.GetImm(b) + 1))) + { + SXTW(CR, gpr.R(a)); + ADD(CR, CR, (~gpr.GetImm(b) + 1) >> 12, true); + } else { ARM64Reg RA = gpr.R(a); |