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authorXTra.KrazzY <XTra.KrazzY@gmail.com>2009-09-24 13:52:45 +0000
committerXTra.KrazzY <XTra.KrazzY@gmail.com>2009-09-24 13:52:45 +0000
commitebfceb16b9192daa907ce50fff7faeb62cedc6de (patch)
treeaaa686712f06e816ebf816a9c31a072865849552 /docs
parent750ad4fb5d031ae83559c8339e69a2e66065a304 (diff)
Some leftover work from unfinished DX9 Access EFB. In DSP HLE, 0x0004,7,b,c are almost done, all that's left to do is resample from 0x50 to _Size.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4313 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'docs')
-rw-r--r--docs/DSP/DSP_UC_Zelda.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/DSP/DSP_UC_Zelda.txt b/docs/DSP/DSP_UC_Zelda.txt
index c74fc94f9b..9202d9d043 100644
--- a/docs/DSP/DSP_UC_Zelda.txt
+++ b/docs/DSP/DSP_UC_Zelda.txt
@@ -3213,7 +3213,7 @@ void 0919_Decoder0x6_Constant(AR0, AX0.L) {
void 091c_Decoder0x7_WaveTable(ACC0, AR0, AX0.L) {
// So AR2 is where it reads the data from, and it updates ACC0 to the final read address in the end
- // Questions: What is IX2 used for? And how does the wrap register change the data access?
+ // Questions: How does the wrap register change the data access?
// 091c 0082 0100 lri $AR2, #0x0100
// 091e 008a 003f lri $WR2, #0x003f