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Requires a minor change to in the JIT to make sure everything still works.
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SMOV doesn't have an encoding for moving a 32bit element to a 32bit GPR.
One should use UMOV if they want that.
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A bit more efficient if we are only pushing two VFP registers.
We can probably be a bit more efficient in the future by mixing paired loadstores in to the other paths as well.
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Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.
On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
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These will be used with the vertex loader JIT recompiler.
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Since I've added the msg handler. I found all these asserts that were backwards. So they were asserting on the correct arguments.
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[AArch64] Implement TU/TL merging.
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These two instructions ignore the register encoded in to RA.
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Adds a bunch of new instructions to the emitter.
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Renames Is128Bit to IsQuad to line up more with the other helpers.
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Use the ZR for both input arguments in the case the immediate is the maximum immediate value.
This allows it to be aliased to MVN when disassembling.
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I wasn't bit shifting correctly for 8 and 16bit loadstores.
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These weren't emitting the flag bit. So they were regular ADD and SUB emitters.
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Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
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In the case of a zero immediate, it wouldn't generate code at all.
Also in the case of max u32/u64, use ORN to optimize it.
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I've tested a few instruction encodings and am expecting most to work as long as one stays away from VFP/SIMD.
This implements mostly instructions to bring up an initial JIT with integer support.
This can be improved to allow ease of use functions in the future, dealing with the raw imms/immr encodings is probably the worst thing ever.
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