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Replace the bool parameter force5bytes in J, JMP, and J_CC with an enum
class Jump::Short/Near. Many callers set that parameter to the literal
'true', which was unclear if you didn't already know what it did.
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SPDX standardizes how source code conveys its copyright and licensing
information. See https://spdx.github.io/spdx-spec/1-rationale/ . SPDX
tags are adopted in many large projects, including things like the Linux
kernel.
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Converts lingering panic alert calls over to the fmt-capable ones.
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Continues the migration of our code over to the fmt logger.
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TODO was already taken care of in PR #941.
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Shorter, displacement is now handled in one location.
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Due to the way the ModRM encoding works on x86, memory addressing
combinations involving RBP or R13 need an additional byte for an 8-bit
displacement of zero.
However, this was also applied in cases where it is unnecessary,
effectively wasting a byte.
- MatR with RSP or R12
8B 44 24 00 mov eax,dword ptr [rsp]
8B 04 24 mov eax,dword ptr [rsp]
- MRegSum with base != RBP or R13
46 8D 7C 37 00 lea r15d,[rdi+r14]
46 8D 3C 37 lea r15d,[rdi+r14]
- MComplex without offset
8B 4C CA 00 mov ecx,dword ptr [rdx+rcx*8]
8B 0C CA mov ecx,dword ptr [rdx+rcx*8]
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Prior to this commit, the emitter would emit a 7-byte instruction when
loading a 32-bit immediate to a 64-bit register.
0: 48 c7 c0 ff ff ff 7f mov rax,0x7fffffff
With this change, it will check if it can instead emit a load to a
32-bit register, which takes only 5 or 6 bytes.
0: b8 ff ff ff 7f mov eax,0x7fffffff
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Jit64: Prefer MOVAPS where possible
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* The high half of regOp is immediately overwritten so the value in it is irrelevant.
* MOVSD produces an unnecessary dependency on the high half of regOp.
* MOVAPS is implemented as a register rename on modern microarchitectures.
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There is no reason to use MOVAPD over MOVAPS, for two reasons:
* There has never been a microarchitecture with separate single and double domains.
* MOVAPD is one byte longer than MOVAPS
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x64Emitter: emit shorter MOVs for 64-bit immediates
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Prior to this commit, the emitter would unconditionally emit a 10-byte
instruction known as MOVABS when loading a 64-bit immediate to a
register.
0: 48 b8 ef be ad de 00 movabs rax,0xdeadbeef
7: 00 00 00
With this change, it will instead rely on the fact that on x64 writes to
32-bit registers are automatically zero extended to 64-bits, allowing
us to emit a 5 or 6-bytes instruction with the same effect for certain
immediates.
0: b8 ef be ad de mov eax,0xdeadbeef
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Prior to this commit, the emitter would unconditionally emit a 10-byte
instruction known as MOVABS when loading a 64-bit immediate to a
register.
0: 48 b8 ef be ad de ff movabs rax,0xffffffffdeadbeef
7: ff ff ff
With this change, it will instead emit a 7-byte instruction when it is
possible to express the 64-bit immediate using a signed 32-bit value.
0: 48 c7 c0 ef be ad de mov rax,0xffffffffdeadbeef
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Gets rid of the use of magic values and replaces them with strongly
typed symbolic names.
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There's no real requirement to make this const, and this should also
be decided by the calling code, considering we had places that would
simply cast away the const and carry on.
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Reduces the amount of identifiers placed in the Gen namespace internally.
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These are only used internally. This also allows us to eliminate some
symbols that get dumped into the exposed Gen namespace.
By extension this also hides the Write[X] functions from OpArg's public
interface. This is only used internally by XEmitter, so they shouldn't
be usable by anything else.
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This brings the macro in line with the regular ASSERT macro, which only has one
macro parameter.
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Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
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Gets rid of the need to cast to void* just to use the functions.
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This optimization broke arithXex in rare cases by
emitting XOR where MOV was expected.
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Replaces incarnations of the A=B+C pattern throughout the
code so we can apply optimizations consistently.
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Simplication to avoid reading back the generated instructions, allowing
us to handle all possible cases.
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No more ubsan asserts in the JIT and x64 emitter code paths when running starfield.
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Now that VS supports more printf specifiers, these aren't necessary
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This also silences quite a few ubsan asserts from firing when the emitter is being used.
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With the exception of BZHI, BMI2 instructions don't affect flags, so
don't check if they're locked.
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Suggested by degasus.
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Considering OpArg is a struct, passing by value creates unnecessary copies.
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