| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-07-27 | docs/DSP: fix some bit pattern inconsistencies | Tillmann Karras | |
| Thanks to @Oaisus who reported this. | |||
| 2025-04-25 | docs/DSP: Rename SCALE to PRED_SCALE | Tillmann Karras | |
| 2025-04-25 | Address Pokechu22's feedback | Tillmann Karras | |
| 2025-04-25 | Update DSP docs with accelerator info, fix ANDC/ORC instruction description ↵ | xperia64 | |
| typos | |||
| 2025-04-25 | Rename accelerator accesses to 'raw' and 'sample' | xperia64 | |
| 2022-09-30 | docs/DSP: Trivial adjustment to BLOOP{,I} sub-operation order | Vincent Pelletier | |
| Noticed while tracing in a BLOOP using DSPSpy with $st{0..3} unmasked. BLOOPI assumed to follow the pattern. | |||
| 2022-06-01 | docs/DSP: Update version and history | Pokechu22 | |
| The GFDL requires the history section to be updated. | |||
| 2022-06-01 | docs/DSP: Explain 16-bit and 40-bit modes | Pokechu22 | |
| 2022-06-01 | docs/DSP: Add notes highlighting the difference between 'LS and 'SL | Pokechu22 | |
| 2022-05-31 | docs/DSP: Add missing dollar signs in shift instruction operation sections | Pokechu22 | |
| 2022-05-29 | docs/DSP: Fix inconsistency with ADDI and CMPI | Pokechu22 | |
| We don't have anything called $amD, though we do have $acsD. However, these instructions affect flags based on the whole accumulator, so it's better to just use $acD. | |||
| 2022-05-29 | docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediate | Pokechu22 | |
| These instructions used an 'r' in their bit list, but a 'd' in the operands. | |||
| 2022-05-29 | docs/DSP: Document the behavior when main and extended opcodes both write to ↵ | Pokechu22 | |
| the same register (the write backlog) For more information, ApplyWriteBackLog, WriteToBackLog, and ZeroWriteBackLog were added in b787f5f8f7709cff763c2f3a13b90455a0c8ee18 and the explanatory comment was added in fd40513fed84e41e4b4b65cb4f98295223bcbd9b, although it did not mention the specific instructions that could trigger this edge case. The statements about which registers can be written by main opcodes and extension opcodes are based on my own checking of all instructions in the manual. | |||
| 2022-05-29 | docs/DSP: Fix typo in 'NOP comment | Pokechu22 | |
| 2022-05-29 | docs/DSP: Clarify LRS note | Pokechu22 | |
| $acS.h was a typo, which has been replaced with $acD.h. | |||
| 2022-05-27 | docs/DSP: Rename CMPAR to CMPAXH | Pokechu22 | |
| 2022-05-21 | docs/DSP: Fix "ILLR" typo in Instruction Memory section | Pokechu22 | |
| 2022-05-14 | Add tested bootloading transfer size | xperia64 | |
| 2021-08-22 | dsp_rom: Add version numbers and hashes to VerifyRoms and readme | Pokechu22 | |
| 2021-08-22 | dsp_rom: Remove illegal use of AX with SRS | Pokechu22 | |
| 2021-08-22 | dsp_rom: add pseudo code and fix small accuracy issues | Tillmann Karras | |
| Doesn't fix anything, hence not upstreaming this. | |||
| 2021-08-22 | dsp_rom: Fix readme eols and trailing whitespace | Pokechu22 | |
| 2021-08-21 | docs/DSP: Update version and history | Pokechu22 | |
| The GFDL requires the history section to be updated. | |||
| 2021-08-21 | docs/DSP: NEG can set overflow and carry | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix typo with MULCMVZ and MULCMV | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document initialization process | Pokechu22 | |
| 2021-08-21 | docs/DSP: A failed RETcc only inceases PC by 1, not 2 | Pokechu22 | |
| This is because RETcc is a single-word instruction. | |||
| 2021-08-21 | docs/DSP: Add RTIcc | Pokechu22 | |
| 2021-08-21 | docs/DSP: Change conditional names to match Dolphin | Pokechu22 | |
| 2021-08-21 | docs/DSP: Split SRSH from SRS | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document behavior of LRS/SRS/SI with CR | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document masking/sign extension behavior of registers | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix registers used by MOVAX and MOV | Pokechu22 | |
| 2021-08-21 | docs/DSP: MADDC operates on acS.m, not acS.l | Pokechu22 | |
| This matches the prose and Dolphin's implementation. | |||
| 2021-08-21 | docs/DSP: Add information about flags for every instruction | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document overflow and carry behavior | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix MULXAC bytes | Pokechu22 | |
| The previous encoding was for MULXMVZ. | |||
| 2021-08-21 | docs/DSP: Fix 'S format | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix 'LS encoding | Pokechu22 | |
| The old encoding was a copy of 'LN. | |||
| 2021-08-21 | docs/DSP: Fix acD/acR conflation in shift instructions | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix operation for LSR/ASR | Pokechu22 | |
| 2021-08-21 | docs/DSP: Note that ADDAXL is unsigned | Pokechu22 | |
| 2021-08-21 | docs/DSP: Fix operation of ADDR and SUBR | Pokechu22 | |
| 2021-08-21 | docs/DSP: Adjust operation for CMPI and CMPIS | Pokechu22 | |
| This more clearly indicates what it is supposed to do. | |||
| 2021-08-21 | docs/DSP: Document rounding behavior of CLRL | Pokechu22 | |
| 2021-08-21 | docs/DSP: Add 'NOP | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document 'LD and 'LDAX | Pokechu22 | |
| 2021-08-21 | docs/DSP: Document behavior and instructions when the first nybble is 3 | Pokechu22 | |
| 2021-08-21 | docs/DSP: Add most missing instructions | Pokechu22 | |
| These instructions were already implememented by Dolphin, but never added to the manual. Extension instructions will be handled in a later commit, as wlil instructions that were not previously implememented by Dolphin. | |||
| 2021-08-21 | docs/DSP: Adjust bit names in opcode table | Pokechu22 | |
| The old names did not match the ones used by the instructions themselves, and were generally fairly inconsistent. | |||
 |
index : dolphin | |
| GameCube and Wii emulator | root |
| summaryrefslogtreecommitdiff |