From fbdf721e0ec00a0b4775c6d70e2724e4ca96a9fd Mon Sep 17 00:00:00 2001
From: Marko Pusljar <LM1234@gmail.com>
Date: Sun, 24 Jan 2010 00:31:20 +0000
Subject: ROM dissasm "refresh" + RE + small fixes

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4938 8ced0084-cf51-0410-be5f-012b33b47a6e
---
 Source/Core/DSPCore/Src/DSPInterpreter.h |  1 +
 Source/Core/DSPCore/Src/DSPTables.cpp    |  1 +
 Source/Core/DSPCore/Src/DspIntMisc.cpp   | 10 ++++++++++
 3 files changed, 12 insertions(+)

(limited to 'Source/Core/DSPCore')

diff --git a/Source/Core/DSPCore/Src/DSPInterpreter.h b/Source/Core/DSPCore/Src/DSPInterpreter.h
index 37d464ea4d..434f46bdde 100644
--- a/Source/Core/DSPCore/Src/DSPInterpreter.h
+++ b/Source/Core/DSPCore/Src/DSPInterpreter.h
@@ -126,6 +126,7 @@ void lsrn(const UDSPInstruction& opc);
 void asrn(const UDSPInstruction& opc);
 void dar(const UDSPInstruction& opc);
 void iar(const UDSPInstruction& opc);
+void xar(const UDSPInstruction& opc);
 void sbclr(const UDSPInstruction& opc);
 void sbset(const UDSPInstruction& opc);
 void mov(const UDSPInstruction& opc);
diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp
index 9eb13527c1..fdb5d9cb27 100644
--- a/Source/Core/DSPCore/Src/DSPTables.cpp
+++ b/Source/Core/DSPCore/Src/DSPTables.cpp
@@ -41,6 +41,7 @@ const DSPOPCTemplate opcodes[] =
 
 	{"DAR",		0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
 	{"IAR",		0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
+	{"XAR",		0x000c, 0xfffc, DSPInterpreter::xar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false},
 
 	{"ADDARN",  0x0010, 0xfff0, DSPInterpreter::addarn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false},
 
diff --git a/Source/Core/DSPCore/Src/DspIntMisc.cpp b/Source/Core/DSPCore/Src/DspIntMisc.cpp
index 8e674f54c4..ce27fd085b 100644
--- a/Source/Core/DSPCore/Src/DspIntMisc.cpp
+++ b/Source/Core/DSPCore/Src/DspIntMisc.cpp
@@ -129,6 +129,16 @@ void iar(const UDSPInstruction& opc)
 	g_dsp.r[opc.hex & 0x3] = dsp_increment_addr_reg(opc.hex & 0x3);
 }
 
+// XAR $arD  ?
+// 0000 0000 0000 11dd
+// $arD result somehow depends on $wrD
+// unknown atm
+// used in IPL ucode
+void xar(const UDSPInstruction& opc)
+{
+//	u8 dreg = opc.hex & 0x3;
+}
+
 // SBCLR #I
 // 0001 0011 0000 0iii
 // bit of status register $sr. Bit number is calculated by adding 6 to
-- 
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