From bc8a4f99c754c13b8e40d88ef012e93934f98125 Mon Sep 17 00:00:00 2001 From: booto Date: Fri, 31 May 2019 02:46:17 -0400 Subject: VideoCommon: Constrain the array_base registers The array_base registers as part of CP state do not seem to incorporate the upper bits in the physical address they try to access. --- Source/Core/VideoCommon/CommandProcessor.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Source/Core/VideoCommon/CommandProcessor.cpp') diff --git a/Source/Core/VideoCommon/CommandProcessor.cpp b/Source/Core/VideoCommon/CommandProcessor.cpp index 897675f4e0..eb571a4672 100644 --- a/Source/Core/VideoCommon/CommandProcessor.cpp +++ b/Source/Core/VideoCommon/CommandProcessor.cpp @@ -138,12 +138,19 @@ void Init() et_UpdateInterrupts = CoreTiming::RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper); } +u32 GetPhysicalAddressMask() +{ + // Physical addresses in CP seem to ignore some of the upper bits (depending on platform) + // This can be observed in CP MMIO registers by setting to 0xffffffff and then reading back. + return SConfig::GetInstance().bWii ? 0x1fffffff : 0x03ffffff; +} + void RegisterMMIO(MMIO::Mapping* mmio, u32 base) { constexpr u16 WMASK_NONE = 0x0000; constexpr u16 WMASK_ALL = 0xffff; constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0; - const u16 WMASK_HI_RESTRICT = SConfig::GetInstance().bWii ? 0x1fff : 0x03ff; + const u16 WMASK_HI_RESTRICT = GetPhysicalAddressMask() >> 16; struct { -- cgit v1.2.3