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<title>yuzu/src/core/arm/nce/arm_nce.cpp, branch main</title>
<subtitle>Nintendo Switch emulator</subtitle>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/'/>
<entry>
<title>android: Update build system and optimize ARM NCE implementation</title>
<updated>2025-05-12T11:46:19+00:00</updated>
<author>
<name>Zephyron</name>
<email>zephyron@citron-emu.org</email>
</author>
<published>2025-03-11T10:48:51+00:00</published>
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<id>c8884fb0399f8e3fdf06b1e4c603bc2320377a26</id>
<content type='text'>
- Update Kotlin from 1.9.20 to 2.1.20-RC2
- Upgrade Java version from 17 to 21
- Update Android Gradle plugin from 8.1.2 to 8.9.0
- Update Gradle wrapper from 8.10.2 to 8.11.1
- Update NDK version to 29.0.13113456 rc1
- Update all Android dependencies to latest versions
- Simplify ARM NCE implementation by removing custom TLB handling
- Improve alignment and access fault handling
- Update hardware BASE_CLOCK_RATE from 1.02GHz to 1.785GHz
- Add citron Emulator Project copyright notices

Signed-off-by: Zephyron &lt;zephyron@citron-emu.org&gt;
</content>
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- Update Kotlin from 1.9.20 to 2.1.20-RC2
- Upgrade Java version from 17 to 21
- Update Android Gradle plugin from 8.1.2 to 8.9.0
- Update Gradle wrapper from 8.10.2 to 8.11.1
- Update NDK version to 29.0.13113456 rc1
- Update all Android dependencies to latest versions
- Simplify ARM NCE implementation by removing custom TLB handling
- Improve alignment and access fault handling
- Update hardware BASE_CLOCK_RATE from 1.02GHz to 1.785GHz
- Add citron Emulator Project copyright notices

Signed-off-by: Zephyron &lt;zephyron@citron-emu.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Improve TLB implementation and fault handling in NCE</title>
<updated>2025-05-12T11:46:19+00:00</updated>
<author>
<name>Zephyron</name>
<email>zephyron@citron-emu.orgq</email>
</author>
<published>2025-02-28T07:11:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/commit/?id=856c00f19c4ddfeb050df05012d3ea7a825e0b07'/>
<id>856c00f19c4ddfeb050df05012d3ea7a825e0b07</id>
<content type='text'>
This commit enhances the Translation Lookaside Buffer (TLB) implementation
in the ARM Native Code Execution (NCE) component to increase stability,
particularly on Android devices. The changes prioritize robustness and
error recovery over performance optimizations.

Key improvements:
- Replace set-associative TLB with a simpler linear search implementation
- Implement a basic LRU replacement policy for TLB entries
- Add validation checks for memory addresses before TLB insertion
- Ensure proper page alignment for guest and host addresses
- Enhance alignment fault handling with instruction skipping as fallback
- Add comprehensive debug logging for memory access errors
- Improve error recovery in guest memory access scenarios

These changes should significantly reduce crashes during emulation on
Android devices by gracefully handling memory access edge cases that
previously resulted in hard crashes.

Co-Authored-By: Camille LaVey &lt;camillelavey@citron-emu.org&gt;
Signed-off-by: Zephyron &lt;zephyron@citron-emu.org&gt;
</content>
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<pre>
This commit enhances the Translation Lookaside Buffer (TLB) implementation
in the ARM Native Code Execution (NCE) component to increase stability,
particularly on Android devices. The changes prioritize robustness and
error recovery over performance optimizations.

Key improvements:
- Replace set-associative TLB with a simpler linear search implementation
- Implement a basic LRU replacement policy for TLB entries
- Add validation checks for memory addresses before TLB insertion
- Ensure proper page alignment for guest and host addresses
- Enhance alignment fault handling with instruction skipping as fallback
- Add comprehensive debug logging for memory access errors
- Improve error recovery in guest memory access scenarios

These changes should significantly reduce crashes during emulation on
Android devices by gracefully handling memory access edge cases that
previously resulted in hard crashes.

Co-Authored-By: Camille LaVey &lt;camillelavey@citron-emu.org&gt;
Signed-off-by: Zephyron &lt;zephyron@citron-emu.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>core/arm/nce: Implement TLB caching system</title>
<updated>2025-05-12T11:46:19+00:00</updated>
<author>
<name>Zephyron</name>
<email>zephyron@citron-emu.orgq</email>
</author>
<published>2025-02-25T08:37:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/commit/?id=d187d7c52c6bdd3a7d845db13f9acaaf48eff86f'/>
<id>d187d7c52c6bdd3a7d845db13f9acaaf48eff86f</id>
<content type='text'>
Adds a software TLB cache to improve memory access performance in the NCE
(Native Code Execution) system. Key changes include:

- Implement set-associative TLB with 64 sets and 8 ways
- Add TLB lookup before memory access in HandleGuestAccessFault
- Implement LRU replacement policy with access frequency consideration
- Add thread context caching to reduce overhead
- Add proper synchronization with mutex locks
- Add helper functions for TLB management (lookup, insert, invalidate)

This change should improve performance by reducing redundant memory
translations and providing faster access to frequently used pages.
</content>
<content type='xhtml'>
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<pre>
Adds a software TLB cache to improve memory access performance in the NCE
(Native Code Execution) system. Key changes include:

- Implement set-associative TLB with 64 sets and 8 ways
- Add TLB lookup before memory access in HandleGuestAccessFault
- Implement LRU replacement policy with access frequency consideration
- Add thread context caching to reduce overhead
- Add proper synchronization with mutex locks
- Add helper functions for TLB management (lookup, insert, invalidate)

This change should improve performance by reducing redundant memory
translations and providing faster access to frequently used pages.
</pre>
</div>
</content>
</entry>
<entry>
<title>nce: increase handler stack size</title>
<updated>2023-12-19T20:24:13+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-12-19T20:24:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/commit/?id=93c19a40bf9b999ad15c66a4afba9bfb0479ba4f'/>
<id>93c19a40bf9b999ad15c66a4afba9bfb0479ba4f</id>
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</entry>
<entry>
<title>nce: adjust initialization for repeated calls</title>
<updated>2023-12-12T04:02:01+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-12-12T04:02:01+00:00</published>
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</entry>
<entry>
<title>nce: implement instruction emulation for misaligned memory accesses</title>
<updated>2023-12-10T23:23:42+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-11-30T19:05:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/commit/?id=bd599343505d202dc3d8226ca80d5f1af0247bf2'/>
<id>bd599343505d202dc3d8226ca80d5f1af0247bf2</id>
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</content>
</entry>
<entry>
<title>core: refactor emulated cpu core activation</title>
<updated>2023-12-04T15:37:16+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-11-28T19:30:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.dog6.net/yuzu/commit/?id=45c87c7e6e841c11def43e5ab25160006dab6d77'/>
<id>45c87c7e6e841c11def43e5ab25160006dab6d77</id>
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</entry>
<entry>
<title>core: Rename patcher file</title>
<updated>2023-11-29T21:49:16+00:00</updated>
<author>
<name>GPUCode</name>
<email>geoster3d@gmail.com</email>
</author>
<published>2023-11-29T21:49:16+00:00</published>
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</entry>
<entry>
<title>arm_nce: skip data aborts for crash handling parity</title>
<updated>2023-11-25T05:47:36+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-11-22T04:23:48+00:00</published>
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</entry>
<entry>
<title>arm_nce: skip dc cvac on possibly write-protected areas</title>
<updated>2023-11-25T05:47:36+00:00</updated>
<author>
<name>Liam</name>
<email>byteslice@airmail.cc</email>
</author>
<published>2023-11-19T18:57:23+00:00</published>
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