yuzu/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp, branch main Nintendo Switch emulator general: Convert source file copyright comments over to SPDX 2022-04-23T09:55:32+00:00 Morph 39850852+Morph1984@users.noreply.github.com 2022-04-23T08:59:50+00:00 99ceb03a1cfcf35968cab589ea188a8c406cda52 This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later. 
This formats all copyright comments according to SPDX formatting guidelines.
Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
shader_recompiler: Adjust emit_context includes 2021-12-05T23:11:19+00:00 ameerj 52414509+ameerj@users.noreply.github.com 2021-12-05T21:42:03+00:00 f32b2bcd200097659d7c6e0dfdef1e96e3f2f69e 






shader: Add integer division opcodes
2021-11-16T21:11:28+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-07-26T00:27:21+00:00

95761cc6a70987b2625d68c4d9da4e2622f57808












opengl: Implement LOP.CC
2021-07-23T01:51:39+00:00

ameerj
52414509+ameerj@users.noreply.github.com

2021-06-25T17:09:45+00:00

8289eb108fefa9bfbb445c9f6b3f423a5d0eb771

Used by MH:Rise





Used by MH:Rise







shader: Remove IAbs64
2021-07-23T01:51:39+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-06-22T21:28:21+00:00

4397053d5c848deae00d6599f91b1e5c137a9639












glasm: Fix INeg32 on negative immediates
2021-07-23T01:51:33+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-05-25T05:48:03+00:00

70c9281fbffbf5f68a267ba85f6e4b3c122fa3ac












glasm: Catch more register leaks
2021-07-23T01:51:33+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-05-25T05:22:21+00:00

ca05a13c62ad7693f8be924c168e400e8139b0d2

Add support for null registers. These are used when an instruction has
no usages.

This comes handy when an instruction is only used for its CC value, with
the caveat of having to invalidate all pseudo-instructions before
defining the instruction itself in the register allocator. This commits
changes this.

Workaround a bug on Nvidia's condition codes conditional execution using
branches.





Add support for null registers. These are used when an instruction has
no usages.

This comes handy when an instruction is only used for its CC value, with
the caveat of having to invalidate all pseudo-instructions before
defining the instruction itself in the register allocator. This commits
changes this.

Workaround a bug on Nvidia's condition codes conditional execution using
branches.







glasm: Implement int64 add and subtract
2021-07-23T01:51:33+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-05-23T23:16:09+00:00

0794273870dfc0ae9c217b6869845debfc8a8792












glasm: Implement 64-bit shifts
2021-07-23T01:51:32+00:00

ReinUsesLisp
reinuseslisp@airmail.cc

2021-05-19T20:09:29+00:00

291f220be37d5fed36906b4fce977a5e4e23f481












glasm: Implement IADD.CC
2021-07-23T01:51:32+00:00

ameerj
52414509+ameerj@users.noreply.github.com

2021-05-19T04:29:07+00:00

3777592ada560e2943a066f7d2d62fd468dbf62c