Initial repo setup (#1)

* git subrepo clone git@github.com:ethteck/splat.git tools/splat

subrepo:
  subdir:   "tools/splat"
  merged:   "4fec014"
upstream:
  origin:   "git@github.com:ethteck/splat.git"
  branch:   "master"
  commit:   "4fec014"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* gitignore

* decompress_baserom.py

* Initial yaml

* run flib

* more yaml stuff

* Builds an uncompressed ROM

* setup ido download

* git subrepo clone git@github.com:simonlindholm/asm-differ.git tools/asm-differ

subrepo:
  subdir:   "tools/asm-differ"
  merged:   "ae40866"
upstream:
  origin:   "git@github.com:simonlindholm/asm-differ.git"
  branch:   "main"
  commit:   "ae40866"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo clone git@github.com:simonlindholm/asm-processor.git tools/asm-processor

subrepo:
  subdir:   "tools/asm-processor"
  merged:   "bbd86ea"
upstream:
  origin:   "git@github.com:simonlindholm/asm-processor.git"
  branch:   "main"
  commit:   "bbd86ea"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo clone (merge) git@github.com:EllipticEllipsis/fado.git tools/fado

subrepo:
  subdir:   "tools/fado"
  merged:   "8d896ee"
upstream:
  origin:   "git@github.com:EllipticEllipsis/fado.git"
  branch:   "master"
  commit:   "8d896ee"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* setup ido in makefile

* data and rodata

* add automatic file splits

* bootstrap most symbol_addrs

* git subrepo clone --branch=irix git@github.com:hensldm/ultralib.git lib/ultralib

subrepo:
  subdir:   "lib/ultralib"
  merged:   "0d1e095"
upstream:
  origin:   "git@github.com:hensldm/ultralib.git"
  branch:   "irix"
  commit:   "0d1e095"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* setup ido building

* various tooling

* git subrepo pull tools/asm-differ

subrepo:
  subdir:   "tools/asm-differ"
  merged:   "857b398"
upstream:
  origin:   "git@github.com:simonlindholm/asm-differ.git"
  branch:   "main"
  commit:   "857b398"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* Change defines to match IDO

* review

* newlin

* update gitignore

* Windows error

* D_01000000

* yeet settings.json

* yeet

* git subrepo clone git@github.com:decompals/ultralib.git lib/ultralib

subrepo:
  subdir:   "lib/ultralib"
  merged:   "d03b2a3"
upstream:
  origin:   "git@github.com:decompals/ultralib.git"
  branch:   "main"
  commit:   "d03b2a3"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* clangformat and clangtidy

* Setup a bunch of headers

* bootstrap boot and code functions and variables headers

* global.h

* update format.py includes

* -D_MIPS_SZLONG=32

* format.py: --verbose

* Update tools/decompress_baserom.py

Co-authored-by: Derek Hensley <hensley.derek58@gmail.com>

* Add libc to global.h

* review

* yeet saved_regs

* yeet headers

* yeet _MSC_VER

* more header cleanup

* add readme licensing note

---------

Co-authored-by: Derek Hensley <hensley.derek58@gmail.com>

1 files changed, 35 insertions, 0 deletions

diff --git a/lib/ultralib/src/os/writebackdcache.s b/lib/ultralib/src/os/writebackdcache.s
new file mode 100644
index 0000000..5f5b485
--- /dev/null
+++ b/lib/ultralib/src/os/writebackdcache.s
@@ -0,0 +1,35 @@
+#include "PR/R4300.h"
+#include "sys/asm.h"
+#include "sys/regdef.h"
+
+.text
+LEAF(osWritebackDCache)
+    blez a1, 2f
+    li t3, DCACHE_SIZE
+    bgeu a1,t3, 3f
+    move t0, a0
+    addu t1, a0,a1
+    bgeu t0, t1, 2f
+    addiu t1, t1, -DCACHE_LINESIZE
+    andi t2, t0, DCACHE_LINEMASK
+    subu t0, t0,t2
+1:
+	.set noreorder
+    cache (C_HWB|CACH_PD), (t0)
+    bltu t0, t1, 1b
+     addiu t0, t0, DCACHE_LINESIZE
+	.set reorder
+2:
+    jr ra
+3:
+    li t0, KUSIZE
+    addu t1, t0,t3
+    addiu t1, t1, -DCACHE_LINESIZE
+4:
+	.set noreorder
+    cache (C_IWBINV|CACH_PD), (t0)
+    bltu t0, t1, 4b
+     addiu t0, t0, DCACHE_LINESIZE
+	.set reorder
+    jr ra
+END(osWritebackDCache)