Update subrepos (#19)

* git subrepo pull --force tools/asm-processor

subrepo:
  subdir:   "tools/asm-processor"
  merged:   "6dd4d3a"
upstream:
  origin:   "git@github.com:simonlindholm/asm-processor.git"
  branch:   "main"
  commit:   "6dd4d3a"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull lib/ultralib --force

subrepo:
  subdir:   "lib/ultralib"
  merged:   "0417857"
upstream:
  origin:   "git@github.com:decompals/ultralib.git"
  branch:   "main"
  commit:   "0417857"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull tools/asm-differ --force

subrepo:
  subdir:   "tools/asm-differ"
  merged:   "6d3e4c4"
upstream:
  origin:   "git@github.com:simonlindholm/asm-differ.git"
  branch:   "main"
  commit:   "6d3e4c4"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* git subrepo pull tools/splat --force

subrepo:
  subdir:   "tools/splat"
  merged:   "406b646"
upstream:
  origin:   "git@github.com:ethteck/splat.git"
  branch:   "master"
  commit:   "406b646"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* Revert "git subrepo pull lib/ultralib --force"

This reverts commit da9fca47be7d8f957b786c02d7bf4b4a48830f4a.

* git subrepo pull tools/splat

subrepo:
  subdir:   "tools/splat"
  merged:   "7869ef2"
upstream:
  origin:   "git@github.com:ethteck/splat.git"
  branch:   "master"
  commit:   "7869ef2"
git-subrepo:
  version:  "0.4.3"
  origin:   "https://github.com/ingydotnet/git-subrepo.git"
  commit:   "2f68596"

* Disable asm size directive

8 files changed, 614 insertions, 16 deletions

diff --git a/tools/asm-differ/.github/workflows/check-poetry-lock.yml b/tools/asm-differ/.github/workflows/check-poetry-lock.yml
new file mode 100644
index 0000000..6104770
--- /dev/null
+++ b/tools/asm-differ/.github/workflows/check-poetry-lock.yml
@@ -0,0 +1,20 @@
+name: flake check
+
+on:
+  pull_request:
+  push:
+
+permissions: read-all
+
+jobs:
+  tests:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      # Install `nix` which is just a dead-simple way to get a stable `poetry`
+      # in scope.
+      - uses: cachix/install-nix-action@v20
+        with:
+          github_access_token: ${{ secrets.GITHUB_TOKEN }}
+      # Check that poetry.lock is in sync with pyproject.toml
+      - run: nix run github:NixOS/nixpkgs/22.11#poetry -- lock --check
diff --git a/tools/asm-differ/.github/workflows/unit-tests.yml b/tools/asm-differ/.github/workflows/unit-tests.yml
new file mode 100644
index 0000000..a77498a
--- /dev/null
+++ b/tools/asm-differ/.github/workflows/unit-tests.yml
@@ -0,0 +1,15 @@
+name: unit tests
+
+on:
+  pull_request:
+  push:
+
+permissions: read-all
+
+jobs:
+  tests:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - run: python3 -m pip install --user colorama watchdog levenshtein cxxfilt
+      - run: python3 test.py
diff --git a/tools/asm-differ/.gitignore b/tools/asm-differ/.gitignore
index a2b216f..90df93b 100644
--- a/tools/asm-differ/.gitignore
+++ b/tools/asm-differ/.gitignore
@@ -1,4 +1,3 @@
 .mypy_cache/
 __pycache__/
 .vscode/
-poetry.lock
diff --git a/tools/asm-differ/.gitrepo b/tools/asm-differ/.gitrepo
index a98d53e..b40f427 100644
--- a/tools/asm-differ/.gitrepo
+++ b/tools/asm-differ/.gitrepo
@@ -6,7 +6,7 @@
 [subrepo]
 	remote = git@github.com:simonlindholm/asm-differ.git
 	branch = main
-	commit = 857b39804a6f764634483cff7adc168a2f3e5c87
-	parent = 6e36168761e33e6c33e6f15c2678733ce61ddffb
+	commit = 6d3e4c44d1ad8ad59bcae3abecb35f0d10e135e1
+	parent = da9fca47be7d8f957b786c02d7bf4b4a48830f4a
 	method = merge
 	cmdver = 0.4.3
diff --git a/tools/asm-differ/README.md b/tools/asm-differ/README.md
index 1d0932c..63b5253 100644
--- a/tools/asm-differ/README.md
+++ b/tools/asm-differ/README.md
@@ -1,6 +1,6 @@
 # asm-differ
 
-Nice differ for assembly code. Currently supports MIPS, PPC, AArch64, and ARM32; should be easy to hack to support other instruction sets.
+Nice differ for assembly code. Currently supports MIPS, PPC, AArch64, ARM32, and SH2; should be easy to hack to support other instruction sets.
 
 ![](screenshot.png)
 
diff --git a/tools/asm-differ/diff.py b/tools/asm-differ/diff.py
index 1b12f9a..543e8fe 100755
--- a/tools/asm-differ/diff.py
+++ b/tools/asm-differ/diff.py
@@ -54,7 +54,7 @@ if __name__ == "__main__":
         argcomplete = None
 
     parser = argparse.ArgumentParser(
-        description="Diff MIPS, PPC, AArch64, or ARM32 assembly."
+        description="Diff MIPS, PPC, AArch64, ARM32, or SH2 assembly."
     )
 
     start_argument = parser.add_argument(
@@ -407,7 +407,7 @@ class ProjectSettings:
     build_command: List[str]
     map_format: str
     build_dir: str
-    ms_map_address_offset: int
+    map_address_offset: int
     baseimg: Optional[str]
     myimg: Optional[str]
     mapfile: Optional[str]
@@ -481,7 +481,9 @@ def create_project_settings(settings: Dict[str, Any]) -> ProjectSettings:
         objdump_flags=settings.get("objdump_flags", []),
         expected_dir=settings.get("expected_dir", "expected/"),
         map_format=settings.get("map_format", "gnu"),
-        ms_map_address_offset=settings.get("ms_map_address_offset", 0),
+        map_address_offset=settings.get(
+            "map_address_offset", settings.get("ms_map_address_offset", 0)
+        ),
         build_dir=settings.get("build_dir", settings.get("mw_build_dir", "build/")),
         show_line_numbers_default=settings.get("show_line_numbers_default", True),
         disassemble_all=settings.get("disassemble_all", False),
@@ -557,6 +559,7 @@ def get_objdump_executable(objdump_executable: Optional[str]) -> str:
         "mips-linux-gnu-objdump",
         "mips64-elf-objdump",
         "mips-elf-objdump",
+        "sh-elf-objdump",
     ]
     for objdump_cand in objdump_candidates:
         try:
@@ -590,7 +593,7 @@ BUFFER_CMD: List[str] = ["tail", "-c", str(10**9)]
 # -i ignores case when searching
 # -c something about how the screen gets redrawn; I don't remember the purpose
 # -#6 makes left/right arrow keys scroll by 6 characters
-LESS_CMD: List[str] = ["less", "-SRic", "-#6"]
+LESS_CMD: List[str] = ["less", "-SRic", "-+F", "-+X", "-#6"]
 
 DEBOUNCE_DELAY: float = 0.1
 
@@ -1270,11 +1273,7 @@ def search_map_file(
         if len(find) == 1:
             names_find = re.search(r"(\S+) ... (\S+)", find[0])
             assert names_find is not None
-            fileofs = (
-                int(names_find.group(1), 16)
-                - load_address
-                + project.ms_map_address_offset
-            )
+            fileofs = int(names_find.group(1), 16) - load_address
             if for_binary:
                 return None, fileofs
 
@@ -1503,6 +1502,7 @@ def dump_binary(
         _, start_addr = search_map_file(start, project, config, for_binary=True)
         if start_addr is None:
             fail("Not able to find function in map file.")
+        start_addr += project.map_address_offset
     if end is not None:
         end_addr = eval_int(end, "End address must be an integer expression.")
     else:
@@ -1568,7 +1568,8 @@ class AsmProcessorMIPS(AsmProcessor):
             # integer.
             return prev, None
         before, imm, after = parse_relocated_line(prev)
-        repl = row.split()[-1] + reloc_addend_from_imm(imm, before, self.config.arch)
+        addend = reloc_addend_from_imm(imm, before, self.config.arch)
+        repl = row.split()[-1] + addend
         if "R_MIPS_LO16" in row:
             repl = f"%lo({repl})"
         elif "R_MIPS_HI16" in row:
@@ -1589,6 +1590,8 @@ class AsmProcessorMIPS(AsmProcessor):
             repl = f"%got({repl})"
         elif "R_MIPS_CALL16" in row:
             repl = f"%call16({repl})"
+        elif "R_MIPS_LITERAL" in row:
+            repl = repl[:-len(addend)]
         else:
             assert False, f"unknown relocation type '{row}' for line '{prev}'"
         return before + repl + after, repl
@@ -1811,6 +1814,17 @@ class AsmProcessorI686(AsmProcessor):
         return mnemonic == "ret"
 
 
+class AsmProcessorSH2(AsmProcessor):
+    def __init__(self, config: Config) -> None:
+        super().__init__(config)
+
+    def process_reloc(self, row: str, prev: str) -> Tuple[str, Optional[str]]:
+        return prev, None
+
+    def is_end_of_function(self, mnemonic: str, args: str) -> bool:
+        return mnemonic == "rts"
+
+
 @dataclass
 class ArchSettings:
     name: str
@@ -2005,6 +2019,15 @@ I686_BRANCH_INSTRUCTIONS = {
     "jz",
 }
 
+SH2_BRANCH_INSTRUCTIONS = {
+    "bf",
+    "bf.s",
+    "bt",
+    "bt.s",
+    "bra",
+    "bsr",
+}
+
 MIPS_SETTINGS = ArchSettings(
     name="mips",
     re_int=re.compile(r"[0-9]+"),
@@ -2126,6 +2149,34 @@ I686_SETTINGS = ArchSettings(
     proc=AsmProcessorI686,
 )
 
+SH2_SETTINGS = ArchSettings(
+    name="sh2",
+    # match -128-127 preceded by a '#' with a ',' after (8 bit immediates)
+    re_int=re.compile(r"(?<=#)(-?(?:1[01][0-9]|12[0-8]|[1-9][0-9]?|0))(?=,)"),
+    # match <text>, match ! and after
+    re_comment=re.compile(r"<.*?>|!.*"),
+    #   - r0-r15 general purpose registers, r15 is stack pointer during exceptions
+    #   - sr, gbr, vbr - control registers
+    #   - mach, macl, pr, pc - system registers
+    re_reg=re.compile(r"r1[0-5]|r[0-9]"),
+    # sh2 has pc-relative and gbr-relative but not stack-pointer-relative
+    re_sprel=re.compile(r"(?<=,)([0-9]+|0x[0-9a-f]+)\(sp\)"),
+    # max immediate size is 8-bit
+    re_large_imm=re.compile(r"-?[1-9][0-9]{2,}|-?0x[0-9a-f]{3,}"),
+    re_imm=re.compile(r"\b0[xX][0-9a-fA-F]+\b"),
+    # https://github.com/bminor/binutils-gdb/blob/master/bfd/elf32-sh-relocs.h#L21
+    re_reloc=re.compile(r"R_SH_"),
+    arch_flags=["-m", "sh2"],
+    branch_instructions=SH2_BRANCH_INSTRUCTIONS,
+    instructions_with_address_immediates=SH2_BRANCH_INSTRUCTIONS.union(
+        {"bf", "bf.s", "bt", "bt.s", "bra", "bsr"}
+    ),
+    delay_slot_instructions=SH2_BRANCH_INSTRUCTIONS.union(
+        {"bf.s", "bt.s", "bra", "braf", "bsr", "bsrf", "jmp", "jsr", "rts"}
+    ),
+    proc=AsmProcessorSH2,
+)
+
 ARCH_SETTINGS = [
     MIPS_SETTINGS,
     MIPSEL_SETTINGS,
@@ -2135,11 +2186,18 @@ ARCH_SETTINGS = [
     AARCH64_SETTINGS,
     PPC_SETTINGS,
     I686_SETTINGS,
+    SH2_SETTINGS,
 ]
 
 
 def hexify_int(row: str, pat: Match[str], arch: ArchSettings) -> str:
     full = pat.group(0)
+
+    # sh2 only has 8-bit immediates, just convert them uniformly without
+    # any -hex stuff
+    if arch.name == "sh2":
+        return hex(int(full) & 0xFF)
+
     if len(full) <= 1:
         # leave one-digit ints alone
         return full
@@ -2497,7 +2555,7 @@ def diff_sequences(
     try:
         rem1 = remap(seq1)
         rem2 = remap(seq2)
-    except ValueError as e:
+    except ValueError:
         if len(seq1) + len(seq2) < 0x110000:
             raise
         # If there are too many unique elements, chr() doesn't work.
@@ -3112,7 +3170,7 @@ def align_diffs(old_diff: Diff, new_diff: Diff, config: Config) -> TableData:
 
     def diff_line_to_table_line(line: Tuple[OutputLine, ...]) -> TableLine:
         cells = [
-            (line[0].base or Text(), line[0].line1)
+            (line[0].base or Text(), line[0].line1),
         ]
         for ol in line[1:]:
             cells.append((ol.fmt2, ol.line2))
diff --git a/tools/asm-differ/poetry.lock b/tools/asm-differ/poetry.lock
new file mode 100644
index 0000000..2826d78
--- /dev/null
+++ b/tools/asm-differ/poetry.lock
@@ -0,0 +1,321 @@
+# This file is automatically @generated by Poetry 1.4.2 and should not be changed by hand.
+
+[[package]]
+name = "ansiwrap"
+version = "0.8.4"
+description = "textwrap, but savvy to ANSI colors and styles"
+category = "main"
+optional = false
+python-versions = "*"
+files = [
+    {file = "ansiwrap-0.8.4-py2.py3-none-any.whl", hash = "sha256:7b053567c88e1ad9eed030d3ac41b722125e4c1271c8a99ade797faff1f49fb1"},
+    {file = "ansiwrap-0.8.4.zip", hash = "sha256:ca0c740734cde59bf919f8ff2c386f74f9a369818cdc60efe94893d01ea8d9b7"},
+]
+
+[package.dependencies]
+textwrap3 = ">=0.9.2"
+
+[[package]]
+name = "colorama"
+version = "0.4.6"
+description = "Cross-platform colored terminal text."
+category = "main"
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
+files = [
+    {file = "colorama-0.4.6-py2.py3-none-any.whl", hash = "sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6"},
+    {file = "colorama-0.4.6.tar.gz", hash = "sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44"},
+]
+
+[[package]]
+name = "cxxfilt"
+version = "0.3.0"
+description = "Python interface to c++filt / abi::__cxa_demangle"
+category = "main"
+optional = false
+python-versions = "*"
+files = [
+    {file = "cxxfilt-0.3.0-py2.py3-none-any.whl", hash = "sha256:774e85a8d0157775ed43276d89397d924b104135762d86b3a95f81f203094e07"},
+    {file = "cxxfilt-0.3.0.tar.gz", hash = "sha256:7df6464ba5e8efbf0d8974c0b2c78b32546676f06059a83515dbdfa559b34214"},
+]
+
+[package.extras]
+test = ["pytest (>=3.0.0)"]
+
+[[package]]
+name = "levenshtein"
+version = "0.20.9"
+description = "Python extension for computing string edit distances and similarities."
+category = "main"
+optional = false
+python-versions = ">=3.6"
+files = [
+    {file = "Levenshtein-0.20.9-cp310-cp310-macosx_10_9_universal2.whl", hash = "sha256:105c239ec786750cd5136991c58196b440cc39b6acf3ec8227f6562c9a94e4b9"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:2f7728bea7fe6dc55ceecde0dcda4287e74fe3b6733ad42530f46aaa8d2f81d0"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-macosx_11_0_arm64.whl", hash = "sha256:cc7eca755c13c92814c8cce8175524cf764ce38f39228b602f59eac58cfdc51a"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:e8a552e79d053dc1324fb90d342447fd4e15736f4cbc5363b6fbd5577f53dce9"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", hash = "sha256:5474b2681ee0b7944fb1e7fe281cd44e2dfe75b03ba4558dca49c96fa0861b62"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:56e132c203b0dd8fc72a33e791c39ad0d5a25bcf24b130a1e202abbf489a3e75"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:3badc94708ac05b405e795fde58a53272b90a9ee6099ecd54a345658b7b812e1"},
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+    {file = "Levenshtein-0.20.9-cp310-cp310-musllinux_1_1_x86_64.whl", hash = "sha256:c554704eec4f4ba742febdcc79a85491f8f9a1d493cb103bb2af18536d6cf122"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-win32.whl", hash = "sha256:7628e356b3f9c78ad7272c3b9137f0641a1368849e749ff6f2c8fe372795806b"},
+    {file = "Levenshtein-0.20.9-cp310-cp310-win_amd64.whl", hash = "sha256:ba2bafe3511194a37044cae4e7d328cca70657933052691c37eba2ca428a379d"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-macosx_10_9_universal2.whl", hash = "sha256:7605a94145198d19fdaaa7e29c0f8a56ad719b12386f3ae8cd8ed4cb9fa6c2e4"},
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+    {file = "Levenshtein-0.20.9-cp311-cp311-macosx_11_0_arm64.whl", hash = "sha256:965336c1772a4fc5fb2686a2a0bfaf3455dced96f19f50f278da8bc139076d31"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:67235753035ac898d6475c0b29540521018db2e0027a3c1deb9aa0af0a84fd74"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", hash = "sha256:120dca58136aee3d8c7b190e30db7b6a6eb9579ea5712df84ad076a389801743"},
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+    {file = "Levenshtein-0.20.9-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:c0af20327acc2c904d11611cb3a0d8d17f80c279a12e0b84189eafc35297186d"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-manylinux_2_5_i686.manylinux1_i686.manylinux_2_17_i686.manylinux2014_i686.whl", hash = "sha256:34d2f891ef53afbab6cf2eeb92ff13151884d17dc80a2d6d3c7ae74d7738b772"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-musllinux_1_1_aarch64.whl", hash = "sha256:2ab9c72380582bf4745d1c5b055b1df0c85f7a980a04bd7603a855dd91478c0f"},
+    {file = "Levenshtein-0.20.9-cp311-cp311-musllinux_1_1_i686.whl", hash = "sha256:6de13be3eb5ac48053fb1635a7b4daa936b9114ad4b264942e9eb709fcaa41dd"},
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+    {file = "watchdog-2.3.1.tar.gz", hash = "sha256:d9f9ed26ed22a9d331820a8432c3680707ea8b54121ddcc9dc7d9f2ceeb36906"},
+]
+
+[package.extras]
+watchmedo = ["PyYAML (>=3.10)"]
+
+[metadata]
+lock-version = "2.0"
+python-versions = "^3.7"
+content-hash = "f48df5c526c5e9e9b6c8dd83bb06b628c347f616a66670800e3032a83ba50c08"
diff --git a/tools/asm-differ/test.py b/tools/asm-differ/test.py
new file mode 100644
index 0000000..c0c2a9c
--- /dev/null
+++ b/tools/asm-differ/test.py
@@ -0,0 +1,185 @@
+import unittest
+import diff
+import json
+
+class TestSh2(unittest.TestCase):
+    def get_config(self):
+        arch = diff.get_arch('sh2')
+        formatter = diff.JsonFormatter(arch_str='sh2')
+        config = diff.Config(
+            arch=arch, 
+            diff_obj=True, 
+            objfile='', 
+            make=False, 
+            source_old_binutils=True, 
+            diff_section='.text', 
+            inlines=False, 
+            max_function_size_lines=25000, 
+            max_function_size_bytes=100000, 
+            formatter=formatter, 
+            diff_mode=diff.DiffMode.NORMAL, 
+            base_shift=0, 
+            skip_lines=0, 
+            compress=None, 
+            show_rodata_refs=True, 
+            show_branches=True,
+            show_line_numbers=False, 
+            show_source=False, 
+            stop_at_ret=False, 
+            ignore_large_imms=False, 
+            ignore_addr_diffs=True, 
+            algorithm='levenshtein', 
+            reg_categories={})
+        return config
+
+    # check that comment <> regex has ? to avoid "<func_060E8780+0x44>,r1      ! 60e87d0"
+    # all being a comment for:
+    # mov.l   44 <func_060E8780+0x44>,r1      ! 60e87d0
+    def test_sh2_comment(self):
+        # parser specifically looks for tabs so make sure they are represented
+
+        # 16:   d1 0b           mov.l   44 <func_060E8780+0x44>,r1      ! 60e87d0
+        sh2_theirs = "  16:\td1 0b       \tmov.l\t44 <func_060E8780+0x44>,r1\t! 60e87d0\n"
+
+        # 16:   d1 0b           mov.l   44 <_func_060E8780+0x44>,r1     ! 0 <_func_060E8780>
+        sh2_ours = "  16:\td1 0b       \tmov.l\t44 <_func_060E8780+0x44>,r1\t! 0 <_func_060E8780>\n"
+
+        config = self.get_config()
+        display = diff.Display(sh2_theirs, sh2_ours, config)
+        loaded = json.loads(display.run_diff()[0])
+
+        curr = loaded['rows'][0]['current']['src_comment']
+
+        assert(curr != "<_func_060E8780+0x44>,r1     ! 0 <_func_060E8780>")
+        assert(curr == "<_func_060E8780+0x44>")
+
+    def test_sh2_immediates(self):
+        # test parsing these immediates
+        # func_0606B760():
+        # 0:   ec 01           mov     #1,r12
+        # 2:   71 01           add     #1,r1
+        # 4:   ec ff           mov     #-1,r12
+        # 6:   71 ff           add     #-1,r1
+        # 8:   ec 7f           mov     #127,r12
+        # a:   71 7f           add     #127,r1
+        # c:   ec 80           mov     #-128,r12
+        # e:   71 80           add     #-128,r1
+        sh2_theirs = 'func_0606B760():\n   0:\tec 01       \tmov\t#1,r12\n   2:\t71 01       \tadd\t#1,r1\n   4:\tec ff       \tmov\t#-1,r12\n   6:\t71 ff       \tadd\t#-1,r1\n   8:\tec 7f       \tmov\t#127,r12\n   a:\t71 7f       \tadd\t#127,r1\n   c:\tec 80       \tmov\t#-128,r12\n   e:\t71 80       \tadd\t#-128,r1'
+
+        # just diff with self
+        sh2_ours = sh2_theirs 
+
+        config = self.get_config()
+        display = diff.Display(sh2_theirs, sh2_ours, config)
+        loaded = json.loads(display.run_diff()[0])
+
+        expected = [
+            "0:    mov     #0x1,r12",
+            "2:    add     #0x1,r1",
+            "4:    mov     #0xff,r12",
+            "6:    add     #0xff,r1",
+            "8:    mov     #0x7f,r12",
+            "a:    add     #0x7f,r1",
+            "c:    mov     #0x80,r12",
+            "e:    add     #0x80,r1"
+        ]
+
+        i = 0
+        for text in loaded['rows']:
+            assert(text['base']['text'][0]['text'] == expected[i])
+            i += 1
+
+    def test_more_sh2_immediates(self):
+        # test that the re_int regex is able to catch all these "boundary" numbers
+        # since we have to match 0-9 one digit at a time
+        #    0:   71 00           add     #0,r1
+        #    2:   71 01           add     #1,r1
+        #    4:   71 09           add     #9,r1
+        #    6:   71 0a           add     #10,r1
+        #    8:   71 0b           add     #11,r1
+        #    a:   71 13           add     #19,r1
+        #    c:   71 64           add     #100,r1
+        #    e:   71 65           add     #101,r1
+        #   10:   71 6d           add     #109,r1
+        #   12:   71 6f           add     #111,r1
+        #   14:   71 77           add     #119,r1
+        #   16:   71 f7           add     #-9,r1
+        #   18:   71 f6           add     #-10,r1
+        #   1a:   71 f5           add     #-11,r1
+        #   1c:   71 ed           add     #-19,r1
+        #   1e:   71 9c           add     #-100,r1
+        #   20:   71 9b           add     #-101,r1
+        #   22:   71 93           add     #-109,r1
+        #   24:   71 91           add     #-111,r1
+        #   26:   71 89           add     #-119,r1
+        sh2_theirs = 'func_0606B760():\n   0:\t71 00       \tadd\t#0,r1\n   2:\t71 01       \tadd\t#1,r1\n   4:\t71 09       \tadd\t#9,r1\n   6:\t71 0a       \tadd\t#10,r1\n   8:\t71 0b       \tadd\t#11,r1\n   a:\t71 13       \tadd\t#19,r1\n   c:\t71 64       \tadd\t#100,r1\n   e:\t71 65       \tadd\t#101,r1\n  10:\t71 6d       \tadd\t#109,r1\n  12:\t71 6f       \tadd\t#111,r1\n  14:\t71 77       \tadd\t#119,r1\n  16:\t71 f7       \tadd\t#-9,r1\n  18:\t71 f6       \tadd\t#-10,r1\n  1a:\t71 f5       \tadd\t#-11,r1\n  1c:\t71 ed       \tadd\t#-19,r1\n  1e:\t71 9c       \tadd\t#-100,r1\n  20:\t71 9b       \tadd\t#-101,r1\n  22:\t71 93       \tadd\t#-109,r1\n  24:\t71 91       \tadd\t#-111,r1\n  26:\t71 89       \tadd\t#-119,r1'
+
+        # just diff with self
+        sh2_ours = sh2_theirs 
+
+        config = self.get_config()
+        display = diff.Display(sh2_theirs, sh2_ours, config)
+        loaded = json.loads(display.run_diff()[0])
+
+        expected = [
+            "0:    add     #0x0,r1",
+            "2:    add     #0x1,r1",
+            "4:    add     #0x9,r1",
+            "6:    add     #0xa,r1",
+            "8:    add     #0xb,r1",
+            "a:    add     #0x13,r1",
+            "c:    add     #0x64,r1",
+            "e:    add     #0x65,r1",
+            "10:    add     #0x6d,r1",
+            "12:    add     #0x6f,r1",
+            "14:    add     #0x77,r1",
+            "16:    add     #0xf7,r1",
+            "18:    add     #0xf6,r1",
+            "1a:    add     #0xf5,r1",
+            "1c:    add     #0xed,r1",
+            "1e:    add     #0x9c,r1",
+            "20:    add     #0x9b,r1",
+            "22:    add     #0x93,r1",
+            "24:    add     #0x91,r1",
+            "26:    add     #0x89,r1"
+        ]
+
+        i = 0
+        for text in loaded['rows']:
+            assert(text['base']['text'][0]['text'] == expected[i])
+            i += 1
+
+    def test_branch(self):
+        # test that bt.s and bra get ~>
+        # func():
+        #    0:   8d 02           bt.s    8 <lab_0606B780>
+        #    2:   6e f3           mov     r15,r14
+        #    4:   a0 01           bra     a <lab_0606B8E0>
+        #    6:   00 09           nop
+
+        # 00000008 <lab_0606B780>:
+        # lab_0606B780():
+        #    8:   db 32           mov.l   d4 <lab_0606B8E0+0xca>,r11
+
+        # 0000000a <lab_0606B8E0>:
+        # lab_0606B8E0():
+        #    a:   00 0b           rts
+        #    c:   00 09           nop
+        sh2_theirs = 'func():\n   0:\t8d 02       \tbt.s\t8 <lab_0606B780>\n   2:\t6e f3       \tmov\tr15,r14\n   4:\ta0 01       \tbra\ta <lab_0606B8E0>\n   6:\t00 09       \tnop\t\n\n00000008 <lab_0606B780>:\nlab_0606B780():\n   8:\tdb 32       \tmov.l\td4 <lab_0606B8E0+0xca>,r11\n\n0000000a <lab_0606B8E0>:\nlab_0606B8E0():\n   a:\t00 0b       \trts\t\n   c:\t00 09       \tnop\t'
+        sh2_ours = sh2_theirs
+
+        config = self.get_config()
+        display = diff.Display(sh2_theirs, sh2_ours, config)
+        loaded = json.loads(display.run_diff()[0])
+
+        # bt.s    8
+        print(loaded['rows'][0]['base']['text'][1]['text'] == '~>')
+        print(loaded['rows'][0]['base']['text'][1]['key'] == '8')
+
+        # bra     a
+        print(loaded['rows'][2]['base']['text'][1]['text'] == '~>')
+        print(loaded['rows'][2]['base']['text'][1]['key'] == '10')
+
+
+if __name__ == '__main__':
+    unittest.main()