diff options
| author | magumagu <magumagu9@gmail.com> | 2014-04-18 20:20:42 -0700 |
|---|---|---|
| committer | magumagu <magumagu9@gmail.com> | 2014-04-18 20:20:42 -0700 |
| commit | 002fb0b5630dcfa2be77d39ddcf29bb538c4d896 (patch) | |
| tree | fa7aa4f41950181b32804c67ca55b9d53555f125 | |
| parent | 68d0a32ef975a72515a7cb6435eebba5b3f44b33 (diff) | |
Interpreter: don't PanicAlert on write to SPR_HID2.
The alert apparently triggers on Midway Arcade Treasures 2; given that the
game otherwise works fine, it's not a high priority to accurately emulate
the bit in question.
Fixes issue 7197.
| -rw-r--r-- | Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp | 26 |
1 files changed, 4 insertions, 22 deletions
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index 7ecca1ab5b..a738e59056 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -293,28 +293,10 @@ void Interpreter::mtspr(UGeckoInstruction _inst) } break; case SPR_HID2: // HID2 - { - UReg_HID2 old_hid2; - old_hid2.Hex = oldValue; - - //if (HID2.LCE && !old_hid2.LCE) - // PanicAlert("Locked cache enabled!"); - - if (HID2.PSE == 0) - PanicAlert("WARNING: PSE (paired single enable) in HID2 was unset"); - - // bool WriteGatherPipeEnable = (bool)HID2.WPE; //TODO? - // bool LockedCacheEnable = (bool)HID2.LCE; - // int DMAQueueLength = HID2.DMAQL; // Ignore - our DMA:s are instantaneous - // bool PairedSingleEnable = HID2.PSE; - // bool QuantizeEnable = HID2.LSQE; - //TODO(ector): Protect LC memory if LCE is false. - //TODO(ector): Honor PSE. - - //_assert_msg_(POWERPC, WriteGatherPipeEnable, "Write gather pipe not enabled!"); - //if ((HID2.PSE == 0)) - // MessageBox(nullptr, "PSE in HID2 is set", "Warning", MB_OK); - } + // TODO: generate illegal instruction for paired inst if PSE or LSQE + // not set. + // TODO: disable write gather pipe if WPE not set + // TODO: emulate locked cache and DMA bits. break; case SPR_WPAR: |