diff options
| author | Bram Speeckaert <bram.speeckaert@guardsquare.com> | 2024-05-04 17:20:18 +0200 |
|---|---|---|
| committer | Bram Speeckaert <bram.speeckaert@guardsquare.com> | 2024-05-07 21:11:49 +0200 |
| commit | 5d647251f71b4241aab41ca929cb0de554c0809e (patch) | |
| tree | 3c1580b2a9831f65f97ae33f97fab12e2a49abff | |
| parent | 2c913674295e08bca0e2cb1726b778fb61bf6bd1 (diff) | |
JitArm64: subfic - Conditionally skip temp reg allocation
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index dd75068064..5ebb84a5c1 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -1392,13 +1392,17 @@ void JitArm64::subfic(UGeckoInstruction inst) } else { - gpr.BindToRegister(d, d == a); + const bool allocate_reg = d == a; + gpr.BindToRegister(d, allocate_reg); // d = imm - a - ARM64Reg WA = gpr.GetReg(); + ARM64Reg RD = gpr.R(d); + ARM64Reg WA = allocate_reg ? gpr.GetReg() : RD; MOVI2R(WA, imm); - CARRY_IF_NEEDED(SUB, SUBS, gpr.R(d), WA, gpr.R(a)); - gpr.Unlock(WA); + CARRY_IF_NEEDED(SUB, SUBS, RD, WA, gpr.R(a)); + + if (allocate_reg) + gpr.Unlock(WA); ComputeCarry(); } |
