summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTilka <tilkax@gmail.com>2020-01-06 13:15:17 +0100
committerGitHub <noreply@github.com>2020-01-06 13:15:17 +0100
commitf17f03ea3cd3fccfcfe18148500c04a37d48a11e (patch)
treef74b923a379719fdd4d8360e7198869305acfb67
parent6e18dfb600016fb47e1593315c480e886b7d80d3 (diff)
parent12fcbac2a32a9b97b72f919a7f25b76dda7532b1 (diff)
Merge pull request #8551 from Sintendo/jit64addx
Jit64: addx optimizations
-rw-r--r--Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp19
1 files changed, 15 insertions, 4 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
index 8eadc3d33f..494969b71f 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
@@ -1330,18 +1330,29 @@ void Jit64::addx(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd);
- if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
+ if (d == a)
{
- LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
+ ADD(32, Rd, Rb);
}
else if (d == b)
{
ADD(32, Rd, Ra);
}
+ else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
+ {
+ LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
+ }
+ else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
+ {
+ LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
+ }
+ else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
+ {
+ LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
+ }
else
{
- if (d != a)
- MOV(32, Rd, Ra);
+ MOV(32, Rd, Ra);
ADD(32, Rd, Rb);
}
if (inst.OE)