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authorJosJuice <josjuice@gmail.com>2023-12-17 17:24:13 +0100
committerJosJuice <josjuice@gmail.com>2023-12-17 18:13:32 +0100
commita8e1e1ae48d0c03f60c3fc7cd13856b92590efc8 (patch)
treeda517f0bb131c34ed69e7a0f2679becfb511e2d8 /Source/Core/Common/Arm64Emitter.cpp
parent630341620128684cb7965a0245d0e5f51af7ed45 (diff)
JitArm64: Optimize additional cases of ANDI2R and friends
Now we'll never need a scratch register for values that are all zeroes or all ones.
Diffstat (limited to 'Source/Core/Common/Arm64Emitter.cpp')
-rw-r--r--Source/Core/Common/Arm64Emitter.cpp23
1 files changed, 22 insertions, 1 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp
index cb34fccb7e..7d7b9fc16f 100644
--- a/Source/Core/Common/Arm64Emitter.cpp
+++ b/Source/Core/Common/Arm64Emitter.cpp
@@ -4045,6 +4045,10 @@ void ARM64XEmitter::ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{
// Do nothing
}
+ else if (imm == 0)
+ {
+ MOVZ(Rd, 0);
+ }
else if (const auto result = LogicalImm(imm, Is64Bit(Rn) ? GPRSize::B64 : GPRSize::B32))
{
AND(Rd, Rn, result);
@@ -4065,6 +4069,10 @@ void ARM64XEmitter::ORRI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{
// Do nothing
}
+ else if (imm == (Is64Bit(Rn) ? 0xFFFF'FFFF'FFFF'FFFF : 0xFFFF'FFFF))
+ {
+ MOVN(Rd, 0);
+ }
else if (const auto result = LogicalImm(imm, Is64Bit(Rn) ? GPRSize::B64 : GPRSize::B32))
{
ORR(Rd, Rn, result);
@@ -4085,6 +4093,10 @@ void ARM64XEmitter::EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{
// Do nothing
}
+ else if (imm == (Is64Bit(Rn) ? 0xFFFF'FFFF'FFFF'FFFF : 0xFFFF'FFFF))
+ {
+ MVN(Rd, Rn);
+ }
else if (const auto result = LogicalImm(imm, Is64Bit(Rn) ? GPRSize::B64 : GPRSize::B32))
{
EOR(Rd, Rn, result);
@@ -4101,7 +4113,16 @@ void ARM64XEmitter::EORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
void ARM64XEmitter::ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch)
{
- if (const auto result = LogicalImm(imm, Is64Bit(Rn) ? GPRSize::B64 : GPRSize::B32))
+ if (imm == 0)
+ {
+ ANDS(Rd, Is64Bit(Rn) ? ARM64Reg::ZR : ARM64Reg::WZR,
+ Is64Bit(Rn) ? ARM64Reg::ZR : ARM64Reg::WZR);
+ }
+ else if (imm == (Is64Bit(Rn) ? 0xFFFF'FFFF'FFFF'FFFF : 0xFFFF'FFFF))
+ {
+ ANDS(Rd, Rn, Rn);
+ }
+ else if (const auto result = LogicalImm(imm, Is64Bit(Rn) ? GPRSize::B64 : GPRSize::B32))
{
ANDS(Rd, Rn, result);
}