diff options
| author | Lioncash <mathew1800@gmail.com> | 2020-12-30 20:24:41 -0500 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2020-12-30 20:49:20 -0500 |
| commit | fab2053439ace33e8a7380ac04ef48c22d3bc421 (patch) | |
| tree | 73b9c8816d5992f6aba8b137bc3a2b41e634d05c /Source/Core/Common/Arm64Emitter.cpp | |
| parent | d87ec716158ac270cd1847d40ab0c28866562638 (diff) | |
Arm64Emitter: Make RoundingMode enum an enum class
Prevents namespace pollution and makes the enum members strongly typed.
Diffstat (limited to 'Source/Core/Common/Arm64Emitter.cpp')
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.cpp | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index 6246ae7b71..ce0820bff8 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -2327,28 +2327,28 @@ void ARM64FloatEmitter::EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, Roundin if (IsGPR(Rd)) { // Use the encoding that transfers the result to a GPR. - bool sf = Is64Bit(Rd); - int type = IsDouble(Rn) ? 1 : 0; + const bool sf = Is64Bit(Rd); + const int type = IsDouble(Rn) ? 1 : 0; Rd = DecodeReg(Rd); Rn = DecodeReg(Rn); int opcode = (sign ? 1 : 0); int rmode = 0; switch (round) { - case ROUND_A: + case RoundingMode::A: rmode = 0; opcode |= 4; break; - case ROUND_P: + case RoundingMode::P: rmode = 1; break; - case ROUND_M: + case RoundingMode::M: rmode = 2; break; - case ROUND_Z: + case RoundingMode::Z: rmode = 3; break; - case ROUND_N: + case RoundingMode::N: rmode = 0; break; } @@ -2363,20 +2363,20 @@ void ARM64FloatEmitter::EmitConvertScalarToInt(ARM64Reg Rd, ARM64Reg Rn, Roundin int opcode = 0; switch (round) { - case ROUND_A: + case RoundingMode::A: opcode = 0x1C; break; - case ROUND_N: + case RoundingMode::N: opcode = 0x1A; break; - case ROUND_M: + case RoundingMode::M: opcode = 0x1B; break; - case ROUND_P: + case RoundingMode::P: opcode = 0x1A; sz |= 2; break; - case ROUND_Z: + case RoundingMode::Z: opcode = 0x1B; sz |= 2; break; |
