diff options
| author | Lioncash <mathew1800@gmail.com> | 2014-11-25 23:12:15 -0500 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2014-11-25 23:27:48 -0500 |
| commit | e9b09a4c9f3e8abf7a234e85d1572fbe814fa40d (patch) | |
| tree | ec8ba7bf849db36bd803ba03d87dac5d5380c983 /Source/Core/Common/ArmEmitter.cpp | |
| parent | 4afb85ef33c39fbda60a92620990e4ae1f2bd763 (diff) | |
Arm(64)Emitter: Make some variables static
Diffstat (limited to 'Source/Core/Common/ArmEmitter.cpp')
| -rw-r--r-- | Source/Core/Common/ArmEmitter.cpp | 80 |
1 files changed, 41 insertions, 39 deletions
diff --git a/Source/Core/Common/ArmEmitter.cpp b/Source/Core/Common/ArmEmitter.cpp index 15ef41044b..dfa808474b 100644 --- a/Source/Core/Common/ArmEmitter.cpp +++ b/Source/Core/Common/ArmEmitter.cpp @@ -543,43 +543,45 @@ void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg // IMM, REG, IMMSREG, RSR // -1 for invalid if the instruction doesn't support that -const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s) - {17, 1, 1, 1}, // EOR(s) - {18, 2, 2, 2}, // SUB(s) - {19, 3, 3, 3}, // RSB(s) - {20, 4, 4, 4}, // ADD(s) - {21, 5, 5, 5}, // ADC(s) - {22, 6, 6, 6}, // SBC(s) - {23, 7, 7, 7}, // RSC(s) - {24, 8, 8, 8}, // TST - {25, 9, 9, 9}, // TEQ - {26, 10, 10, 10}, // CMP - {27, 11, 11, 11}, // CMN - {28, 12, 12, 12}, // ORR(s) - {29, 13, 13, 13}, // MOV(s) - {30, 14, 14, 14}, // BIC(s) - {31, 15, 15, 15}, // MVN(s) - {24, -1, -1, -1}, // MOVW - {26, -1, -1, -1}, // MOVT - }; - -const char *InstNames[] = {"AND", - "EOR", - "SUB", - "RSB", - "ADD", - "ADC", - "SBC", - "RSC", - "TST", - "TEQ", - "CMP", - "CMN", - "ORR", - "MOV", - "BIC", - "MVN" - }; +static const s32 InstOps[][4] = { + {16, 0, 0, 0}, // AND(s) + {17, 1, 1, 1}, // EOR(s) + {18, 2, 2, 2}, // SUB(s) + {19, 3, 3, 3}, // RSB(s) + {20, 4, 4, 4}, // ADD(s) + {21, 5, 5, 5}, // ADC(s) + {22, 6, 6, 6}, // SBC(s) + {23, 7, 7, 7}, // RSC(s) + {24, 8, 8, 8}, // TST + {25, 9, 9, 9}, // TEQ + {26, 10, 10, 10}, // CMP + {27, 11, 11, 11}, // CMN + {28, 12, 12, 12}, // ORR(s) + {29, 13, 13, 13}, // MOV(s) + {30, 14, 14, 14}, // BIC(s) + {31, 15, 15, 15}, // MVN(s) + {24, -1, -1, -1}, // MOVW + {26, -1, -1, -1}, // MOVT +}; + +static const char* InstNames[] = { + "AND", + "EOR", + "SUB", + "RSB", + "ADD", + "ADC", + "SBC", + "RSC", + "TST", + "TEQ", + "CMP", + "CMN", + "ORR", + "MOV", + "BIC", + "MVN" +}; void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); } void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); } @@ -774,7 +776,7 @@ void ARMXEmitter::SVC(Operand2 op) // IMM, REG, IMMSREG, RSR // -1 for invalid if the instruction doesn't support that -const s32 LoadStoreOps[][4] = { +static const s32 LoadStoreOps[][4] = { {0x40, 0x60, 0x60, -1}, // STR {0x41, 0x61, 0x61, -1}, // LDR {0x44, 0x64, 0x64, -1}, // STRB @@ -785,7 +787,7 @@ const s32 LoadStoreOps[][4] = { { 0x5, 0x1, -1, -1}, // LDRSB { 0x5, 0x1, -1, -1}, // LDRSH }; -const char *LoadStoreNames[] = { +static const char* LoadStoreNames[] = { "STR", "LDR", "STRB", |