diff options
| author | XTra.KrazzY <XTra.KrazzY@gmail.com> | 2008-11-22 12:10:35 +0000 |
|---|---|---|
| committer | XTra.KrazzY <XTra.KrazzY@gmail.com> | 2008-11-22 12:10:35 +0000 |
| commit | 145f80fc0025ea293cb400e4f2c243ff008714cd (patch) | |
| tree | 2c6cb932af7554d924ab2882878b7ec5e3858ff4 /Source/Core/Common/Src | |
| parent | fb2b57a47c7dcdbd0b2313343cd81cf8a9354357 (diff) | |
Committing magumagu9's work on IMUL JIT
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1241 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/Common/Src')
| -rw-r--r-- | Source/Core/Common/Src/x64Emitter.cpp | 58 | ||||
| -rw-r--r-- | Source/Core/Common/Src/x64Emitter.h | 4 |
2 files changed, 61 insertions, 1 deletions
diff --git a/Source/Core/Common/Src/x64Emitter.cpp b/Source/Core/Common/Src/x64Emitter.cpp index bfefa3e28f..1324cb7761 100644 --- a/Source/Core/Common/Src/x64Emitter.cpp +++ b/Source/Core/Common/Src/x64Emitter.cpp @@ -936,6 +936,64 @@ namespace Gen void CMP (int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmCMP, a1, a2);}
void XCHG(int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmXCHG, a1, a2);}
+ void IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
+ {
+ if (bits == 8) {
+ _assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
+ return;
+ }
+ if (a1.IsImm()) {
+ _assert_msg_(DYNA_REC, 0, "IMUL - second arg cannot be imm!");
+ return;
+ }
+ if (!a2.IsImm())
+ {
+ _assert_msg_(DYNA_REC, 0, "IMUL - third arg must be imm!");
+ return;
+ }
+
+ if (bits == 16)
+ Write8(0x66);
+ a1.WriteRex(bits == 64, regOp);
+
+ if (a2.GetImmBits() == 8) {
+ Write8(0x6B);
+ a1.WriteRest(1, regOp);
+ Write8((u8)a2.offset);
+ } else {
+ Write8(0x69);
+ if (a2.GetImmBits() == 16 && bits == 16) {
+ a1.WriteRest(2, regOp);
+ Write16((u16)a2.offset);
+ } else if (a2.GetImmBits() == 32 &&
+ (bits == 32 || bits == 64)) {
+ a1.WriteRest(4, regOp);
+ Write32((u32)a2.offset);
+ } else {
+ _assert_msg_(DYNA_REC, 0, "IMUL - unhandled case!");
+ }
+ }
+ }
+
+ void IMUL(int bits, X64Reg regOp, OpArg a)
+ {
+ if (bits == 8) {
+ _assert_msg_(DYNA_REC, 0, "IMUL - illegal bit size!");
+ return;
+ }
+ if (a.IsImm())
+ {
+ IMUL(bits, regOp, R(regOp), a) ;
+ return ;
+ }
+
+ if (bits == 16)
+ Write8(0x66);
+ a.WriteRex(bits == 64, regOp);
+ Write8(0x0F);
+ Write8(0xAF);
+ a.WriteRest(0, regOp);
+ }
void WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0)
diff --git a/Source/Core/Common/Src/x64Emitter.h b/Source/Core/Common/Src/x64Emitter.h index 5126aa1d66..b62b24f786 100644 --- a/Source/Core/Common/Src/x64Emitter.h +++ b/Source/Core/Common/Src/x64Emitter.h @@ -282,7 +282,9 @@ namespace Gen void DIV(int bits, OpArg src);
void IMUL(int bits, OpArg src); //SIGNED
void IDIV(int bits, OpArg src);
- //TODO: alternate IMUL forms
+ void IMUL(int bits, X64Reg regOp, OpArg src);
+ void IMUL(int bits, X64Reg regOp, OpArg src, OpArg imm);
+
void NEG(int bits, OpArg src);
void NOT(int bits, OpArg src);
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