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| author | Mat M <mathew1800@gmail.com> | 2018-12-26 09:33:06 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-26 09:33:06 -0500 |
| commit | bd527e62ef69a8c8741fcbc1261c22cbdfe7e7e5 (patch) | |
| tree | b7bfe2a7e9f1af3f0ddf67973fc1cedd9a8ec631 /Source/Core/Common/x64Emitter.cpp | |
| parent | d1ce8aca9d4fe144aeb5951ddeee68cbf220833c (diff) | |
| parent | da7608ff9fbebfcb31a3a16d082ae6e44c46a135 (diff) | |
Merge pull request #7647 from MerryMage/emit-singles
x64Emitter: Add some single-precision instructions
Diffstat (limited to 'Source/Core/Common/x64Emitter.cpp')
| -rw-r--r-- | Source/Core/Common/x64Emitter.cpp | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Source/Core/Common/x64Emitter.cpp b/Source/Core/Common/x64Emitter.cpp index f18ea9fd3a..eb756c3793 100644 --- a/Source/Core/Common/x64Emitter.cpp +++ b/Source/Core/Common/x64Emitter.cpp @@ -2823,6 +2823,38 @@ void XEmitter::PSHUFHW(X64Reg regOp, const OpArg& arg, u8 shuffle) } // VEX +void XEmitter::VADDSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0xF3, sseADD, regOp1, regOp2, arg); +} +void XEmitter::VSUBSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0xF3, sseSUB, regOp1, regOp2, arg); +} +void XEmitter::VMULSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0xF3, sseMUL, regOp1, regOp2, arg); +} +void XEmitter::VDIVSS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0xF3, sseDIV, regOp1, regOp2, arg); +} +void XEmitter::VADDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0x00, sseADD, regOp1, regOp2, arg); +} +void XEmitter::VSUBPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0x00, sseSUB, regOp1, regOp2, arg); +} +void XEmitter::VMULPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0x00, sseMUL, regOp1, regOp2, arg); +} +void XEmitter::VDIVPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0x00, sseDIV, regOp1, regOp2, arg); +} void XEmitter::VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0xF2, sseADD, regOp1, regOp2, arg); @@ -2864,11 +2896,20 @@ void XEmitter::VCMPPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 compare WriteAVXOp(0x66, sseCMP, regOp1, regOp2, arg, 0, 1); Write8(compare); } +void XEmitter::VSHUFPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle) +{ + WriteAVXOp(0x00, sseSHUF, regOp1, regOp2, arg, 0, 1); + Write8(shuffle); +} void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle) { WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 0, 1); Write8(shuffle); } +void XEmitter::VUNPCKLPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) +{ + WriteAVXOp(0x00, 0x14, regOp1, regOp2, arg); +} void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg); @@ -2881,6 +2922,16 @@ void XEmitter::VBLENDVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, X64Reg { WriteAVXOp4(0x66, 0x3A4B, regOp1, regOp2, arg, regOp3); } +void XEmitter::VBLENDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend) +{ + WriteAVXOp(0x66, 0x3A0C, regOp1, regOp2, arg, 0, 1); + Write8(blend); +} +void XEmitter::VBLENDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 blend) +{ + WriteAVXOp(0x66, 0x3A0D, regOp1, regOp2, arg, 0, 1); + Write8(blend); +} void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { |