diff options
| author | Léo Lam <leo@leolam.fr> | 2021-09-20 15:37:57 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-20 15:37:57 +0200 |
| commit | 6129290d3188f9f38ee045f809ec2cb890b3dcab (patch) | |
| tree | 0e086a1c1662a5ce524e7d9343a36b680ed4529b /Source/Core/Common | |
| parent | a25f4fab205e517eaf046ac44ce15d698ff0e405 (diff) | |
| parent | feefc17b023cda2d5c012d8b5b1a5ca019a3d717 (diff) | |
Merge pull request #10057 from JosJuice/jitarm64-divwx
JitArm64: Optimize divwx
Diffstat (limited to 'Source/Core/Common')
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.cpp | 4 | ||||
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.h | 9 |
2 files changed, 13 insertions, 0 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index ce3c0a5103..c0d19f652f 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -1373,6 +1373,10 @@ void ARM64XEmitter::CMP(ARM64Reg Rn, u32 imm, bool shift) { EncodeAddSubImmInst(1, true, shift, imm, Rn, Is64Bit(Rn) ? ARM64Reg::SP : ARM64Reg::WSP); } +void ARM64XEmitter::CMN(ARM64Reg Rn, u32 imm, bool shift) +{ + EncodeAddSubImmInst(0, true, shift, imm, Rn, Is64Bit(Rn) ? ARM64Reg::SP : ARM64Reg::WSP); +} // Data Processing (Immediate) void ARM64XEmitter::MOVZ(ARM64Reg Rd, u32 imm, ShiftAmount pos) diff --git a/Source/Core/Common/Arm64Emitter.h b/Source/Core/Common/Arm64Emitter.h index a5a4c03e4e..5ea860a77a 100644 --- a/Source/Core/Common/Arm64Emitter.h +++ b/Source/Core/Common/Arm64Emitter.h @@ -896,7 +896,15 @@ public: CSINV(Rd, zr, zr, (CCFlags)((u32)cond ^ 1)); } void NEG(ARM64Reg Rd, ARM64Reg Rs) { SUB(Rd, Is64Bit(Rd) ? ARM64Reg::ZR : ARM64Reg::WZR, Rs); } + void NEG(ARM64Reg Rd, ARM64Reg Rs, ArithOption Option) + { + SUB(Rd, Is64Bit(Rd) ? ARM64Reg::ZR : ARM64Reg::WZR, Rs, Option); + } void NEGS(ARM64Reg Rd, ARM64Reg Rs) { SUBS(Rd, Is64Bit(Rd) ? ARM64Reg::ZR : ARM64Reg::WZR, Rs); } + void NEGS(ARM64Reg Rd, ARM64Reg Rs, ArithOption Option) + { + SUBS(Rd, Is64Bit(Rd) ? ARM64Reg::ZR : ARM64Reg::WZR, Rs, Option); + } // Data-Processing 1 source void RBIT(ARM64Reg Rd, ARM64Reg Rn); void REV16(ARM64Reg Rd, ARM64Reg Rn); @@ -1006,6 +1014,7 @@ public: void SUB(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false); void SUBS(ARM64Reg Rd, ARM64Reg Rn, u32 imm, bool shift = false); void CMP(ARM64Reg Rn, u32 imm, bool shift = false); + void CMN(ARM64Reg Rn, u32 imm, bool shift = false); // Data Processing (Immediate) void MOVZ(ARM64Reg Rd, u32 imm, ShiftAmount pos = ShiftAmount::Shift0); |