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authorTillmann Karras <tilkax@gmail.com>2015-01-14 23:31:00 +0100
committerTillmann Karras <tilkax@gmail.com>2015-01-18 13:29:34 +0100
commite80b657cf46879f6a45ac7166b52f8430ac3d85a (patch)
tree6316cfe3cf4f434e6c646d29a3dd8262cc87dd19 /Source/Core/Common
parente82e9f97f5ce2d73d2c8168c7a11504925fd4085 (diff)
Move MOVBE wrappers directly into XEmitter class
Diffstat (limited to 'Source/Core/Common')
-rw-r--r--Source/Core/Common/x64Emitter.cpp27
-rw-r--r--Source/Core/Common/x64Emitter.h2
2 files changed, 29 insertions, 0 deletions
diff --git a/Source/Core/Common/x64Emitter.cpp b/Source/Core/Common/x64Emitter.cpp
index 850a63b293..618ec40b18 100644
--- a/Source/Core/Common/x64Emitter.cpp
+++ b/Source/Core/Common/x64Emitter.cpp
@@ -890,6 +890,33 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, OpArg arg)
void XEmitter::MOVBE(int bits, X64Reg dest, const OpArg& src) {WriteMOVBE(bits, 0xF0, dest, src);}
void XEmitter::MOVBE(int bits, const OpArg& dest, X64Reg src) {WriteMOVBE(bits, 0xF1, src, dest);}
+void XEmitter::LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src)
+{
+ if (cpu_info.bMOVBE)
+ {
+ MOVBE(size, dst, src);
+ }
+ else
+ {
+ MOV(size, R(dst), src);
+ BSWAP(size, dst);
+ }
+}
+
+void XEmitter::SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src)
+{
+ if (cpu_info.bMOVBE)
+ {
+ MOVBE(size, dst, src);
+ }
+ else
+ {
+ BSWAP(size, src);
+ MOV(size, dst, R(src));
+ }
+}
+
+
void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
{
_assert_msg_(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
diff --git a/Source/Core/Common/x64Emitter.h b/Source/Core/Common/x64Emitter.h
index 00536dca34..48a1eae3b1 100644
--- a/Source/Core/Common/x64Emitter.h
+++ b/Source/Core/Common/x64Emitter.h
@@ -479,6 +479,8 @@ public:
// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
void MOVBE(int bits, X64Reg dest, const OpArg& src);
void MOVBE(int bits, const OpArg& dest, X64Reg src);
+ void LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src);
+ void SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src);
// Available only on AMD >= Phenom or Intel >= Haswell
void LZCNT(int bits, X64Reg dest, OpArg src);