diff options
| author | Marko Pusljar <LM1234@gmail.com> | 2010-02-27 21:24:25 +0000 |
|---|---|---|
| committer | Marko Pusljar <LM1234@gmail.com> | 2010-02-27 21:24:25 +0000 |
| commit | ff8ce634e38e960234281134d668631439b17ab2 (patch) | |
| tree | 3b1ce123f0c603ae21f8d5a54c218588cdedfc14 /Source/Core/DSPCore/Src/DSPIntExtOps.cpp | |
| parent | 0425ff2f065e0d2c553e404296333ac0900b7afc (diff) | |
DSPLLE - addaxl,mulc,'ln fix
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5138 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore/Src/DSPIntExtOps.cpp')
| -rw-r--r-- | Source/Core/DSPCore/Src/DSPIntExtOps.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp index 9e623fffdf..e707c4750d 100644 --- a/Source/Core/DSPCore/Src/DSPIntExtOps.cpp +++ b/Source/Core/DSPCore/Src/DSPIntExtOps.cpp @@ -121,7 +121,6 @@ void l(const UDSPInstruction& opc) u8 sreg = opc.hex & 0x3; u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0; - // 40bit sign extension if target is acm.D (important for zelda type ucodes) if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) { u16 val = dsp_dmem_read(g_dsp.r[sreg]); @@ -146,8 +145,19 @@ void ln(const UDSPInstruction& opc) u8 sreg = opc.hex & 0x3; u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0; - writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg])); - writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg])); + if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)) + { + u16 val = dsp_dmem_read(g_dsp.r[sreg]); + writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000); + writeToBackLog(1, dreg, val); + writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0); + writeToBackLog(3, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg])); + } + else + { + writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg])); + writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg])); + } } // LS $axD.l, $acS.m |