diff options
| author | nakeee <nakeee@gmail.com> | 2009-04-22 19:08:13 +0000 |
|---|---|---|
| committer | nakeee <nakeee@gmail.com> | 2009-04-22 19:08:13 +0000 |
| commit | 89178f411cf1e8ef61b005197545618e53a0d4e8 (patch) | |
| tree | 052430c3a2c4660d43b696a980ca07e42f520bd4 /Source/Core/DSPCore/Src/DSPInterpreter.cpp | |
| parent | e3c4e040e9a2f7d39f7e277fcdf4d7cf6909c693 (diff) | |
DSP switched mode 16 and 40
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3045 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore/Src/DSPInterpreter.cpp')
| -rw-r--r-- | Source/Core/DSPCore/Src/DSPInterpreter.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/Source/Core/DSPCore/Src/DSPInterpreter.cpp b/Source/Core/DSPCore/Src/DSPInterpreter.cpp index b7e0162cbb..774da08cbb 100644 --- a/Source/Core/DSPCore/Src/DSPInterpreter.cpp +++ b/Source/Core/DSPCore/Src/DSPInterpreter.cpp @@ -1468,7 +1468,7 @@ void srbith(const UDSPInstruction& opc) // 15-bit precision? clamping? no idea :(
// CLR15 seems to be the default.
- // nakee: It seems to come around mul operation, and it explains what sets the mul bit. But if so why not set/clr14?
+ // It seems to come around mul operation,
case 0xc: // CLR15
g_dsp.r[DSP_REG_SR] &= ~SR_TOP_BIT_UNK;
break;
@@ -1479,12 +1479,12 @@ void srbith(const UDSPInstruction& opc) // 40-bit precision? clamping? no idea :(
// 40 seems to be the default.
// Confirmed these by using DSPSpy and copying the value of SR to R00 after setting.
- case 0xe: // SET40 (really, clear SR's 0x4000) something about "set 40-bit operation"?
- g_dsp.r[DSP_REG_SR] &= ~SR_16_BIT;
+ case 0xe: // SET16 (really, clear SR's 0x4000)
+ g_dsp.r[DSP_REG_SR] &= ~SR_40_MODE_BIT;
break;
- case 0xf: // SET16 (really, set SR's 0x4000) something about "set 16-bit operation"?
- g_dsp.r[DSP_REG_SR] |= SR_16_BIT;
+ case 0xf: // SET40 (really, set SR's 0x4000)
+ g_dsp.r[DSP_REG_SR] |= SR_40_MODE_BIT;
break;
default:
|