diff options
| author | hrydgard <hrydgard@gmail.com> | 2009-06-21 12:09:17 +0000 |
|---|---|---|
| committer | hrydgard <hrydgard@gmail.com> | 2009-06-21 12:09:17 +0000 |
| commit | 37375c711571fc515dc6c0b227c3edf3f4eb44c4 (patch) | |
| tree | 3ba1383689b3f57569a7bf9cf0256b97577769d2 /Source/Core/DSPCore/Src/DspIntArithmetic.cpp | |
| parent | 1ca874365b3bfe6d0ab6d8cbfbc1d34fa37abdeb (diff) | |
Implement the newly discovered DSP opcodes that I named LSRN and ASRN. Also (attempt to) implement reading ARAM through 0xFFD3, like the zelda ucode does.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3523 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore/Src/DspIntArithmetic.cpp')
| -rw-r--r-- | Source/Core/DSPCore/Src/DspIntArithmetic.cpp | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp index 4fb0ef1236..3be4cbba17 100644 --- a/Source/Core/DSPCore/Src/DspIntArithmetic.cpp +++ b/Source/Core/DSPCore/Src/DspIntArithmetic.cpp @@ -652,6 +652,46 @@ void asr(const UDSPInstruction& opc) Update_SR_Register64(acc);
}
+
+// (NEW)
+// LSRN (fixed parameters)
+// 0000 0010 1100 1010
+// Logically shifts right accumulator $ACC0 by signed 16-bit value $AC1.M
+// (if value negative, becomes left shift).
+void lsrn(const UDSPInstruction& opc)
+{
+ s16 shift = (s16)g_dsp.r[DSP_REG_ACM1];
+ u64 acc = dsp_get_long_acc(0);
+ // Lop off the extraneous sign extension our 64-bit fake accum causes
+ acc &= 0x000000FFFFFFFFFFULL;
+ if (shift > 0) {
+ acc >>= shift;
+ } else if (shift < 0) {
+ acc <<= -shift;
+ }
+ dsp_set_long_acc(0, (s64)acc);
+ Update_SR_Register64(acc);
+}
+
+// (NEW)
+// ASRN (fixed parameters)
+// 0000 0010 1100 1010
+// Arithmetically shifts right accumulator $ACC0 by signed 16-bit value $AC1.M
+// (if value negative, becomes left shift).
+void asrn(const UDSPInstruction& opc)
+{
+ s16 shift = (s16)g_dsp.r[DSP_REG_ACM1];
+ s64 acc = dsp_get_long_acc(0);
+ if (shift > 0) {
+ acc >>= shift;
+ } else if (shift < 0) {
+ acc <<= -shift;
+ }
+ dsp_set_long_acc(0, acc);
+ Update_SR_Register64(acc);
+}
+
+
// CMPAR $acS axR.h
// 1100 0001 xxxx xxxx
// Compares accumulator $acS with accumulator axR.h.
|