diff options
| author | nakeee <nakeee@gmail.com> | 2009-08-19 21:37:24 +0000 |
|---|---|---|
| committer | nakeee <nakeee@gmail.com> | 2009-08-19 21:37:24 +0000 |
| commit | b787f5f8f7709cff763c2f3a13b90455a0c8ee18 (patch) | |
| tree | 8d1a7431315b2f6eef45d32e413eecda108f9b0f /Source/Core/DSPCore/Src/DspIntLoadStore.cpp | |
| parent | 8155439dd10afe4eac39d40315fa85cbdee7be53 (diff) | |
DSPLLE: attempt to fix extended ops please review this patch carefully.
thinks to note
- All ext commands should call zeroWriteBackLog() (before changing any
reg)
- increase/decrease ar functions now only return a value not actually
change anything
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4018 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore/Src/DspIntLoadStore.cpp')
| -rw-r--r-- | Source/Core/DSPCore/Src/DspIntLoadStore.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp index d0e50dd278..975ef3bccd 100644 --- a/Source/Core/DSPCore/Src/DspIntLoadStore.cpp +++ b/Source/Core/DSPCore/Src/DspIntLoadStore.cpp @@ -115,7 +115,7 @@ void lrrd(const UDSPInstruction& opc) u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); dsp_conditional_extend_accum(dreg); - dsp_decrement_addr_reg(sreg); + g_dsp.r[sreg] = dsp_decrement_addr_reg(sreg); } // LRRI $D, @$S @@ -131,7 +131,7 @@ void lrri(const UDSPInstruction& opc) u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); dsp_conditional_extend_accum(dreg); - dsp_increment_addr_reg(sreg); + g_dsp.r[sreg] = dsp_increment_addr_reg(sreg); } // LRRN $D, @$S @@ -147,7 +147,7 @@ void lrrn(const UDSPInstruction& opc) u16 val = dsp_dmem_read(dsp_op_read_reg(sreg)); dsp_op_write_reg(dreg, val); dsp_conditional_extend_accum(dreg); - dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]); + g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]); } // SRR @$D, $S @@ -176,7 +176,7 @@ void srrd(const UDSPInstruction& opc) u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); - dsp_decrement_addr_reg(dreg); + g_dsp.r[sreg] = dsp_decrement_addr_reg(dreg); } // SRRI @$D, $S @@ -191,7 +191,7 @@ void srri(const UDSPInstruction& opc) u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); - dsp_increment_addr_reg(dreg); + g_dsp.r[dreg] = dsp_increment_addr_reg(dreg); } // SRRN @$D, $S @@ -206,7 +206,7 @@ void srrn(const UDSPInstruction& opc) u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); - dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]); + g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]); } // ILRR $acD.m, @$arS @@ -234,7 +234,7 @@ void ilrrd(const UDSPInstruction& opc) g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); - dsp_decrement_addr_reg(reg); + g_dsp.r[reg] = dsp_decrement_addr_reg(reg); } // ILRRI $acD.m, @$S @@ -248,7 +248,7 @@ void ilrri(const UDSPInstruction& opc) g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); - dsp_increment_addr_reg(reg); + g_dsp.r[reg] = dsp_increment_addr_reg(reg); } // ILRRN $acD.m, @$arS @@ -263,7 +263,7 @@ void ilrrn(const UDSPInstruction& opc) g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]); dsp_conditional_extend_accum(dreg); - dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]); + g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]); } } // namespace |