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authorhrydgard <hrydgard@gmail.com>2009-06-21 12:09:17 +0000
committerhrydgard <hrydgard@gmail.com>2009-06-21 12:09:17 +0000
commit37375c711571fc515dc6c0b227c3edf3f4eb44c4 (patch)
tree3ba1383689b3f57569a7bf9cf0256b97577769d2 /Source/Core/DSPCore/Src/gdsp_interface.cpp
parent1ca874365b3bfe6d0ab6d8cbfbc1d34fa37abdeb (diff)
Implement the newly discovered DSP opcodes that I named LSRN and ASRN. Also (attempt to) implement reading ARAM through 0xFFD3, like the zelda ucode does.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3523 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore/Src/gdsp_interface.cpp')
-rw-r--r--Source/Core/DSPCore/Src/gdsp_interface.cpp18
1 files changed, 10 insertions, 8 deletions
diff --git a/Source/Core/DSPCore/Src/gdsp_interface.cpp b/Source/Core/DSPCore/Src/gdsp_interface.cpp
index 9a7fb823a0..8693b2ef36 100644
--- a/Source/Core/DSPCore/Src/gdsp_interface.cpp
+++ b/Source/Core/DSPCore/Src/gdsp_interface.cpp
@@ -173,26 +173,28 @@ void gdsp_ifx_write(u16 addr, u16 val)
}
}
-
u16 gdsp_ifx_read(u16 addr)
{
switch (addr & 0xff)
{
- case 0xfc: // DMBH
+ case 0xfc: // DMBH
return gdsp_mbox_read_h(GDSP_MBOX_DSP);
- case 0xfe: // CMBH
+ case 0xfe: // CMBH
return gdsp_mbox_read_h(GDSP_MBOX_CPU);
- case 0xff: // CMBL
+ case 0xff: // CMBL
return gdsp_mbox_read_l(GDSP_MBOX_CPU);
case 0xc9:
return gdsp_ifx_regs[addr & 0xFF];
- case 0xdd:
- // ERROR_LOG(DSPLLE, "Accelerator");
- return dsp_read_aram();
+ case 0xdd: // ADPCM Accelerator reads
+ return dsp_read_accelerator();
+
+ case 0xd3:
+ ERROR_LOG(DSPLLE, "DSP read aram D3");
+ return dsp_read_aram_d3();
default:
if ((addr & 0xff) >= 0xa0) {
@@ -210,7 +212,6 @@ u16 gdsp_ifx_read(u16 addr)
}
}
-
void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
{
UnWriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
@@ -235,6 +236,7 @@ void gdsp_idma_out(u16 dsp_addr, u32 addr, u32 size)
}
+// TODO: These should eat clock cycles.
void gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
{
if ((addr & 0x7FFFFFFF) > 0x01FFFFFF)