diff options
| author | nakeee <nakeee@gmail.com> | 2009-04-16 00:06:37 +0000 |
|---|---|---|
| committer | nakeee <nakeee@gmail.com> | 2009-04-16 00:06:37 +0000 |
| commit | 0801abdcc84ef420afd0b8eeacd98ff7093e9eb5 (patch) | |
| tree | 5c030473ed119d44a750ee5f0089d862f906a0c3 /Source/Core/DSPCore | |
| parent | 19cdbb3e1540e729c1103de7bbd76d7f7f7abf92 (diff) | |
small cleanup
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2978 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore')
| -rw-r--r-- | Source/Core/DSPCore/Src/gdsp_condition_codes.cpp | 11 | ||||
| -rw-r--r-- | Source/Core/DSPCore/Src/gdsp_condition_codes.h | 9 | ||||
| -rw-r--r-- | Source/Core/DSPCore/Src/gdsp_registers.h | 9 |
3 files changed, 15 insertions, 14 deletions
diff --git a/Source/Core/DSPCore/Src/gdsp_condition_codes.cpp b/Source/Core/DSPCore/Src/gdsp_condition_codes.cpp index cdd7c5974a..40eadebfac 100644 --- a/Source/Core/DSPCore/Src/gdsp_condition_codes.cpp +++ b/Source/Core/DSPCore/Src/gdsp_condition_codes.cpp @@ -83,19 +83,20 @@ void Update_SR_LZ(s64 value) { // If this always returns 1, Hermes' demo sounds better.
// However, most AX games are negatively affected.
+// nakee: It seems to be enough to start the bit with 1 to fix Hermes' demo without breaking
+// anything. I also can't seem to find what sets that bit, sbset is called with 0/2/3/5/6
+// and sbclr with 0/2-6 (14 requires 8). Also trying to print when the register is set to 1
+// didn't seem to give any result.
int GetMultiplyModifier()
{
- if (g_dsp.r[DSP_REG_SR] & (1 << 13))
+ if (g_dsp.r[DSP_REG_SR] & SR_MUL_MODIFY)
return 1;
else
return 2;
}
-// 0x02 - overflow????
-// 0x04 - Zero bit
-// 0x08 - Sign bit
-// 0x40 - Logical Zero bit
+//see gdsp_registers.h for flags
bool CheckCondition(u8 _Condition)
{
bool taken = false;
diff --git a/Source/Core/DSPCore/Src/gdsp_condition_codes.h b/Source/Core/DSPCore/Src/gdsp_condition_codes.h index 5e95d00c4e..1cb34bcf88 100644 --- a/Source/Core/DSPCore/Src/gdsp_condition_codes.h +++ b/Source/Core/DSPCore/Src/gdsp_condition_codes.h @@ -31,15 +31,6 @@ namespace DSPInterpreter { // SR flag defines.
#define SR_CMP_MASK 0x3f // Shouldn't this include 0x40?
-// These are probably not accurate. Do not use yet.
-#define SR_UNKNOWN 0x0002 // ????????
-#define SR_ARITH_ZERO 0x0004
-#define SR_SIGN 0x0008
-#define SR_TOP2BITS 0x0020 // this is an odd one.
-#define SR_LOGIC_ZERO 0x0040 // ?? duddie's doc sometimes say & 1<<6 (0x40), sometimes 1<<14 (0x4000), while we have 0x20 .. eh
-#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
-#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2
-
bool CheckCondition(u8 _Condition);
int GetMultiplyModifier();
diff --git a/Source/Core/DSPCore/Src/gdsp_registers.h b/Source/Core/DSPCore/Src/gdsp_registers.h index bd611cf02a..383ac5be66 100644 --- a/Source/Core/DSPCore/Src/gdsp_registers.h +++ b/Source/Core/DSPCore/Src/gdsp_registers.h @@ -92,6 +92,15 @@ #define DSP_STACK_C 0 #define DSP_STACK_D 1 +// These are probably not accurate. Do not use yet. +#define SR_UNKNOWN 0x0002 // ???????? +#define SR_ARITH_ZERO 0x0004 +#define SR_SIGN 0x0008 +#define SR_TOP2BITS 0x0020 // this is an odd one. +#define SR_LOGIC_ZERO 0x0040 // ?? duddie's doc sometimes say & 1<<6 (0x40), sometimes 1<<14 (0x4000), while we have 0x20 .. eh +#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so. +#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 + void dsp_reg_store_stack(u8 stack_reg, u16 val); u16 dsp_reg_load_stack(u8 stack_reg); |
