diff options
| author | hrydgard <hrydgard@gmail.com> | 2009-06-21 06:56:44 +0000 |
|---|---|---|
| committer | hrydgard <hrydgard@gmail.com> | 2009-06-21 06:56:44 +0000 |
| commit | 80217a6ed718d15c75784090340cd3ddd9432f96 (patch) | |
| tree | 79381fe311441d839836fb589b0215277e90eea3 /Source/Core/DSPCore | |
| parent | b7e5fb6ef2f944a2923049f77860988c89ae9216 (diff) | |
DSP: Fix the invalid memory accesses that the Zelda Ucode does in LLE. No LLE sound yet but at least no crazy errors :p
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3516 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core/DSPCore')
| -rw-r--r-- | Source/Core/DSPCore/Src/DspIntMisc.cpp | 6 | ||||
| -rw-r--r-- | Source/Core/DSPCore/Src/gdsp_opcodes_helper.h | 14 |
2 files changed, 19 insertions, 1 deletions
diff --git a/Source/Core/DSPCore/Src/DspIntMisc.cpp b/Source/Core/DSPCore/Src/DspIntMisc.cpp index ef1680321b..732739c0f1 100644 --- a/Source/Core/DSPCore/Src/DspIntMisc.cpp +++ b/Source/Core/DSPCore/Src/DspIntMisc.cpp @@ -97,7 +97,11 @@ void addarn(const UDSPInstruction& opc) u8 dreg = opc.hex & 0x3;
u8 sreg = (opc.hex >> 2) & 0x3;
- g_dsp.r[dreg] += (s16)g_dsp.r[DSP_REG_IX0 + sreg];
+ // g_dsp.r[dreg] += (s16)g_dsp.r[DSP_REG_IX0 + sreg];
+
+ dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
+
+ // It is critical for the Zelda ucode that this one wraps correctly.
}
// NX
diff --git a/Source/Core/DSPCore/Src/gdsp_opcodes_helper.h b/Source/Core/DSPCore/Src/gdsp_opcodes_helper.h index 00f8d7c6b7..2936c1f512 100644 --- a/Source/Core/DSPCore/Src/gdsp_opcodes_helper.h +++ b/Source/Core/DSPCore/Src/gdsp_opcodes_helper.h @@ -82,6 +82,20 @@ inline void dsp_increment_addr_reg(int reg) g_dsp.r[reg]++; } +inline void dsp_increase_addr_reg(int reg, s16 value) +{ + // TODO: DO RIGHT! + if (value > 0) { + for (int i = 0; i < value; i++) { + dsp_increment_addr_reg(reg); + } + } else if (value < 0) { + for (int i = 0; i < (int)(-value); i++) { + dsp_decrement_addr_reg(reg); + } + } +} + // --------------------------------------------------------------------------------------- // --- reg |
