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| author | Sintendo <3380580+Sintendo@users.noreply.github.com> | 2026-10-21 23:54:53 +0200 |
|---|---|---|
| committer | Sintendo <3380580+Sintendo@users.noreply.github.com> | 2026-10-24 19:00:43 +0200 |
| commit | 9c60ba938cce5deb0a6e97769d0456cd2b58f7c3 (patch) | |
| tree | eeaf57b11b26e64dc625e7b014a6b0e611877b01 /Source/Core/InputCommon/ControllerInterface/DualShockUDPClient | |
| parent | c12121f419c40f99eeb65a9039d9fc95be72e94a (diff) | |
VertexLoaderARM64: Optimize RGB565
This replaces the old instruction sequence with one that is considerably
shorter. Main ideas are as follows:
- Use AND with constant mask to isolate the needed bits.
- Use ORR + LSL/LSR to shift the bits into position and combine in one
instruction where possible.
- Red and blue are already sequential, so don't need to wait for the
byteswap. This is especially handy for red, where the bits are
already where they need to be.
- Red and blue can be expanded from 5 to 8 bits together.
Before:
ldurh w14, [x0, #0x1]
rev16 w14, w14
and w15, w14, #0x1f
orr w15, wzr, w15, lsl #3
orr w15, w15, w15, lsr #5
orr w16, wzr, w15, lsl #16
ubfx w15, w14, #5, #6
orr w15, wzr, w15, lsl #2
orr w15, w15, w15, lsr #6
orr w16, w16, w15, lsl #8
ubfx w15, w14, #11, #5
orr w16, w16, w15, lsl #3
orr w16, w16, w15, lsr #2
orr w16, w16, #0xff000000
str w16, [x1, #0xc]
After:
ldurh w14, [x0, #0x1]
rev16 w15, w14
bfi w14, w14, #11, #13
and w16, w14, #0xf800f8
and w14, w14, #0xe000e0
orr w16, w16, #0xff000000
orr w16, w16, w14, lsr #5
and w14, w15, #0x7e0
and w15, w15, #0x600
orr w14, w14, w15, lsr #6
orr w16, w16, w14, lsl #5
str w16, [x1, #0xc]
Diffstat (limited to 'Source/Core/InputCommon/ControllerInterface/DualShockUDPClient')
0 files changed, 0 insertions, 0 deletions
