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authorJosJuice <josjuice@gmail.com>2025-12-07 15:52:31 +0100
committerJosJuice <josjuice@gmail.com>2025-12-08 23:19:10 +0100
commitfca27c375a530a8a589ff47c3408be8b411d0b8c (patch)
tree4c4d9e8c2f48b1bfc6c9316c9aedbf93d48b97d4 /Source/Core/VideoCommon/GraphicsModSystem/Config
parent213dc1c9afb4979dab357327387ab49ce17f174a (diff)
Jit64: Explicitly get imm for clobbered stores
If we're on an x64 CPU that doesn't have the MOVBE extension, trying to SwapAndStore a host register results in that register's value getting clobbered with the swapped value. Jit64::stX and Jit64::stXx detect this case, and if necessary, emit a MOV to a register that's fine to clobber. This logic was broken by the merge of PR 12134. Jit64::stX and Jit64::stXx were assuming that if RegCache::IsImm returns true for a guest register, calling RegCache::Use or RegCache::BindOrImm for that guest register would result in an immediate. However, PR 12134 made it possible for a guest register to have both a host register and an immediate in the register cache at the same time. When this happens, RegCache::IsImm returns true, yet RegCache::Use and RegCache::BindForImm return an RCOpArg whose Location returns a host register. (To make it extra confusing, RCOpArg::IsImm calls RegCache::IsImm if the RCOpArg came from RegCache, so RCOpArg::IsImm returns true!) To fix this, in cases where Jit64::stX and Jit64::stXx explicitly need an immediate to avoid having to emit an extra MOV, let's call RegCache::Imm32 so that we're certain that we're getting an immediate. This fixes an issue on older x64 CPUs that manifested as e.g. completely broken graphics in Spyro: Enter the Dragonfly.
Diffstat (limited to 'Source/Core/VideoCommon/GraphicsModSystem/Config')
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