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| author | JosJuice <josjuice@gmail.com> | 2021-09-04 12:33:32 +0200 |
|---|---|---|
| committer | JosJuice <josjuice@gmail.com> | 2021-09-04 12:48:45 +0200 |
| commit | ea1210773c1ee95b2a3437419285c86be1827d1d (patch) | |
| tree | 5327d10173eb31f6183bc3bbbb68e1ae42278e5c /Source/Core/VideoCommon/PixelEngine.cpp | |
| parent | 755c599c83073e4343bc5372be7c565b587fda1e (diff) | |
JitArm64: Fix W0 being present twice in register cache
Fixes a regression from ecf86bb.
The GPR allocation_order is initialized with only 28 elements,
so the 29th element ends up getting zero initialized.
Very sneaky bug...
Diffstat (limited to 'Source/Core/VideoCommon/PixelEngine.cpp')
0 files changed, 0 insertions, 0 deletions