Merge pull request #11166 from AdmiralCurtiss/mmio-system

HW: Pass System to MMIO handlers.

2 files changed, 96 insertions, 72 deletions

diff --git a/Source/Core/VideoCommon/CommandProcessor.cpp b/Source/Core/VideoCommon/CommandProcessor.cpp
index a5e5591276..ada2d02904 100644
--- a/Source/Core/VideoCommon/CommandProcessor.cpp
+++ b/Source/Core/VideoCommon/CommandProcessor.cpp
@@ -239,7 +239,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
                    MMIO::InvalidWrite<u16>());
   }
 
-  mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
+  mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](Core::System&, u32) {
                    Fifo::SyncGPUForRegisterAccess();
                    SetCpStatusRegister();
                    return m_CPStatusReg.Hex;
@@ -247,7 +247,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
                  MMIO::InvalidWrite<u16>());
 
   mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex),
-                 MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                 MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
                    UCPCtrlReg tmp(val);
                    m_CPCtrlReg.Hex = tmp.Hex;
                    SetCpControlRegister();
@@ -255,7 +255,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
                  }));
 
   mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex),
-                 MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                 MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
                    UCPClearReg tmp(val);
                    m_CPClearReg.Hex = tmp.Hex;
                    SetCpClearRegister();
@@ -265,79 +265,103 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
   mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
 
   // Some MMIOs have different handlers for single core vs. dual core mode.
-  mmio->Register(
-      base | FIFO_RW_DISTANCE_LO,
-      IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
-        if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
-            fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
-        {
-          return static_cast<u16>(fifo.CPWritePointer.load(std::memory_order_relaxed) -
-                                  fifo.SafeCPReadPointer.load(std::memory_order_relaxed));
-        }
-        else
-        {
-          return static_cast<u16>(fifo.CPEnd.load(std::memory_order_relaxed) -
-                                  fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
-                                  fifo.CPWritePointer.load(std::memory_order_relaxed) -
-                                  fifo.CPBase.load(std::memory_order_relaxed) + 32);
-        }
-      }) :
-                     MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
-      MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
-                             WMASK_LO_ALIGN_32BIT));
-  mmio->Register(base | FIFO_RW_DISTANCE_HI,
-                 IsOnThread() ?
-                     MMIO::ComplexRead<u16>([](u32) {
-                       Fifo::SyncGPUForRegisterAccess();
-                       if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
-                           fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
-                       {
-                         return (fifo.CPWritePointer.load(std::memory_order_relaxed) -
-                                 fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
-                                16;
-                       }
-                       else
-                       {
-                         return (fifo.CPEnd.load(std::memory_order_relaxed) -
-                                 fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
-                                 fifo.CPWritePointer.load(std::memory_order_relaxed) -
-                                 fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
-                                16;
-                       }
-                     }) :
-                     MMIO::ComplexRead<u16>([](u32) {
-                       Fifo::SyncGPUForRegisterAccess();
-                       return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
-                     }),
-                 MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
+  const bool is_on_thread = IsOnThread();
+  MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_lo_r;
+  if (is_on_thread)
+  {
+    fifo_rw_distance_lo_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
+      if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
+          fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
+      {
+        return static_cast<u16>(fifo.CPWritePointer.load(std::memory_order_relaxed) -
+                                fifo.SafeCPReadPointer.load(std::memory_order_relaxed));
+      }
+      else
+      {
+        return static_cast<u16>(fifo.CPEnd.load(std::memory_order_relaxed) -
+                                fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
+                                fifo.CPWritePointer.load(std::memory_order_relaxed) -
+                                fifo.CPBase.load(std::memory_order_relaxed) + 32);
+      }
+    });
+  }
+  else
+  {
+    fifo_rw_distance_lo_r = MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance));
+  }
+  mmio->Register(base | FIFO_RW_DISTANCE_LO, fifo_rw_distance_lo_r,
+                 MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
+                                        WMASK_LO_ALIGN_32BIT));
+
+  MMIO::ReadHandlingMethod<u16>* fifo_rw_distance_hi_r;
+  if (is_on_thread)
+  {
+    fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
+      Fifo::SyncGPUForRegisterAccess();
+      if (fifo.CPWritePointer.load(std::memory_order_relaxed) >=
+          fifo.SafeCPReadPointer.load(std::memory_order_relaxed))
+      {
+        return (fifo.CPWritePointer.load(std::memory_order_relaxed) -
+                fifo.SafeCPReadPointer.load(std::memory_order_relaxed)) >>
+               16;
+      }
+      else
+      {
+        return (fifo.CPEnd.load(std::memory_order_relaxed) -
+                fifo.SafeCPReadPointer.load(std::memory_order_relaxed) +
+                fifo.CPWritePointer.load(std::memory_order_relaxed) -
+                fifo.CPBase.load(std::memory_order_relaxed) + 32) >>
+               16;
+      }
+    });
+  }
+  else
+  {
+    fifo_rw_distance_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
+      Fifo::SyncGPUForRegisterAccess();
+      return fifo.CPReadWriteDistance.load(std::memory_order_relaxed) >> 16;
+    });
+  }
+  mmio->Register(base | FIFO_RW_DISTANCE_HI, fifo_rw_distance_hi_r,
+                 MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
                    Fifo::SyncGPUForRegisterAccess();
                    WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
                    Fifo::RunGpu();
                  }));
+
   mmio->Register(
       base | FIFO_READ_POINTER_LO,
-      IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
+      is_on_thread ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
                      MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
       MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
-  mmio->Register(base | FIFO_READ_POINTER_HI,
-                 IsOnThread() ? MMIO::ComplexRead<u16>([](u32) {
-                   Fifo::SyncGPUForRegisterAccess();
-                   return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
-                 }) :
-                                MMIO::ComplexRead<u16>([](u32) {
-                                  Fifo::SyncGPUForRegisterAccess();
-                                  return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
-                                }),
-                 IsOnThread() ? MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
-                   Fifo::SyncGPUForRegisterAccess();
-                   WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
-                   fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
-                                                std::memory_order_relaxed);
-                 }) :
-                                MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
-                                  Fifo::SyncGPUForRegisterAccess();
-                                  WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
-                                }));
+
+  MMIO::ReadHandlingMethod<u16>* fifo_read_hi_r;
+  MMIO::WriteHandlingMethod<u16>* fifo_read_hi_w;
+  if (is_on_thread)
+  {
+    fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
+      Fifo::SyncGPUForRegisterAccess();
+      return fifo.SafeCPReadPointer.load(std::memory_order_relaxed) >> 16;
+    });
+    fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
+      Fifo::SyncGPUForRegisterAccess();
+      WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
+      fifo.SafeCPReadPointer.store(fifo.CPReadPointer.load(std::memory_order_relaxed),
+                                   std::memory_order_relaxed);
+    });
+  }
+  else
+  {
+    fifo_read_hi_r = MMIO::ComplexRead<u16>([](Core::System&, u32) {
+      Fifo::SyncGPUForRegisterAccess();
+      return fifo.CPReadPointer.load(std::memory_order_relaxed) >> 16;
+    });
+    fifo_read_hi_w = MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](Core::System&, u32, u16 val) {
+      Fifo::SyncGPUForRegisterAccess();
+      WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
+    });
+  }
+  mmio->Register(base | FIFO_READ_POINTER_HI, fifo_read_hi_r, fifo_read_hi_w);
 }
 
 void GatherPipeBursted()
diff --git a/Source/Core/VideoCommon/PixelEngine.cpp b/Source/Core/VideoCommon/PixelEngine.cpp
index c110ffa284..af8a7a01c2 100644
--- a/Source/Core/VideoCommon/PixelEngine.cpp
+++ b/Source/Core/VideoCommon/PixelEngine.cpp
@@ -242,11 +242,11 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
   };
   for (auto& pq_reg : pq_regs)
   {
-    mmio->Register(base | pq_reg.addr, MMIO::ComplexRead<u16>([pq_reg](u32) {
+    mmio->Register(base | pq_reg.addr, MMIO::ComplexRead<u16>([pq_reg](Core::System&, u32) {
                      return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) & 0xFFFF;
                    }),
                    MMIO::InvalidWrite<u16>());
-    mmio->Register(base | (pq_reg.addr + 2), MMIO::ComplexRead<u16>([pq_reg](u32) {
+    mmio->Register(base | (pq_reg.addr + 2), MMIO::ComplexRead<u16>([pq_reg](Core::System&, u32) {
                      return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) >> 16;
                    }),
                    MMIO::InvalidWrite<u16>());
@@ -254,7 +254,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
 
   // Control register
   mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.hex),
-                 MMIO::ComplexWrite<u16>([](u32, u16 val) {
+                 MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
                    UPECtrlReg tmpCtrl{.hex = val};
 
                    if (tmpCtrl.pe_token)
@@ -278,7 +278,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
   // BBOX registers, readonly and need to update a flag.
   for (int i = 0; i < 4; ++i)
   {
-    mmio->Register(base | (PE_BBOX_LEFT + 2 * i), MMIO::ComplexRead<u16>([i](u32) {
+    mmio->Register(base | (PE_BBOX_LEFT + 2 * i), MMIO::ComplexRead<u16>([i](Core::System&, u32) {
                      g_renderer->BBoxDisable();
                      return g_video_backend->Video_GetBoundingBox(i);
                    }),