diff options
| author | degasus <wickmarkus@web.de> | 2015-08-08 17:23:52 +0200 |
|---|---|---|
| committer | degasus <wickmarkus@web.de> | 2015-08-24 18:33:23 +0200 |
| commit | 0d92c8fb89d949f12eecbabf65989b1ebc9e2e37 (patch) | |
| tree | 14fdbea8faf682bd81b66b5578cd2465addc4899 /Source/Core | |
| parent | ac84d6d0fa7c47543db8e6704c23583c051cc89c (diff) | |
Jit64: Optimize dcbx
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp | 15 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/JitCommon/JitCache.h | 1 |
2 files changed, 9 insertions, 7 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp index c3f89a9002..8e3e1cff11 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp @@ -313,15 +313,13 @@ void Jit64::dcbx(UGeckoInstruction inst) ADD(32, R(addr), gpr.R(inst.RA)); } - MOV(32, R(value), R(addr)); - SHL(32, R(value), Imm8(3)); - SHR(32, R(value), Imm8(13)); + // Check whether a JIT cache line needs to be invalidated. + LEA(32, value, MScaled(addr, SCALE_8, 0)); // addr << 3 (masks the first 3 bits) + SHR(32, R(value), Imm8(3 + 5 + 5)); // >> 5 for cache line size, >> 5 for width of bitset MOV(64, R(tmp), ImmPtr(jit->GetBlockCache()->GetBlockBitSet())); MOV(32, R(value), MComplex(tmp, value, SCALE_4, 0)); - - MOV(32, R(tmp), R(addr)); - SHR(32, R(tmp), Imm8(5)); - BT(32, R(value), R(tmp)); + SHR(32, R(addr), Imm8(5)); + BT(32, R(value), R(addr)); FixupBranch c = J_CC(CC_C, true); SwitchToFarCode(); @@ -329,6 +327,7 @@ void Jit64::dcbx(UGeckoInstruction inst) BitSet32 registersInUse = CallerSavedRegistersInUse(); ABI_PushRegistersAndAdjustStack(registersInUse, 0); MOV(32, R(ABI_PARAM1), R(addr)); + SHL(32, R(ABI_PARAM1), Imm8(5)); MOV(32, R(ABI_PARAM2), Imm32(32)); XOR(32, R(ABI_PARAM3), R(ABI_PARAM3)); ABI_CallFunction((void*)JitInterface::InvalidateICache); @@ -340,11 +339,13 @@ void Jit64::dcbx(UGeckoInstruction inst) // dcbi if (inst.SUBOP10 == 470) { + // Flush DSP DMA if DMAState bit is set TEST(16, M(&DSP::g_dspState), Imm16(1 << 9)); c = J_CC(CC_NZ, true); SwitchToFarCode(); SetJumpTarget(c); ABI_PushRegistersAndAdjustStack(registersInUse, 0); + SHL(32, R(addr), Imm8(5)); ABI_CallFunctionR((void*)DSP::FlushInstantDMA, addr); ABI_PopRegistersAndAdjustStack(registersInUse, 0); c = J(true); diff --git a/Source/Core/Core/PowerPC/JitCommon/JitCache.h b/Source/Core/Core/PowerPC/JitCommon/JitCache.h index 47408f6c7c..af0580ac85 100644 --- a/Source/Core/Core/PowerPC/JitCommon/JitCache.h +++ b/Source/Core/Core/PowerPC/JitCommon/JitCache.h @@ -66,6 +66,7 @@ public: VALID_BLOCK_MASK_SIZE = 0x20000000 / 32, VALID_BLOCK_ALLOC_ELEMENTS = VALID_BLOCK_MASK_SIZE / 32 }; + // Directly accessed by Jit64. std::unique_ptr<u32[]> m_valid_block; ValidBlockBitSet() |