diff options
| author | MerryMage <MerryMage@users.noreply.github.com> | 2018-10-15 21:01:34 +0100 |
|---|---|---|
| committer | MerryMage <MerryMage@users.noreply.github.com> | 2018-10-28 17:57:44 +0000 |
| commit | 0e501e5c36062ae2a3d4a004cf7a884c681c8be4 (patch) | |
| tree | d7b91ec8e24d5d202d04e35f2866e0f77f2efda3 /Source/Core | |
| parent | 534db3b2ed34e5a13691b902c8f14ce951bedbf1 (diff) | |
Jit_LoadStore: dcbx
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp index a41a83f5a2..0710809506 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp @@ -269,10 +269,12 @@ void Jit64::dcbx(UGeckoInstruction inst) X64Reg addr = RSCRATCH; X64Reg value = RSCRATCH2; - X64Reg tmp = gpr.GetFreeXReg(); - gpr.FlushLockX(tmp); + RCOpArg Ra = inst.RA ? gpr.Use(inst.RA, RCMode::Read) : RCOpArg::Imm32(0); + RCOpArg Rb = gpr.Use(inst.RB, RCMode::Read); + RCX64Reg tmp = gpr.Scratch(gpr.GetFreeXReg()); + RegCache::Realize(Ra, Rb, tmp); - MOV_sum(32, addr, inst.RA ? gpr.R(inst.RA) : Imm32(0), gpr.R(inst.RB)); + MOV_sum(32, addr, Ra, Rb); // Check whether a JIT cache line needs to be invalidated. LEA(32, value, MScaled(addr, SCALE_8, 0)); // addr << 3 (masks the first 3 bits) @@ -297,8 +299,6 @@ void Jit64::dcbx(UGeckoInstruction inst) c = J(true); SwitchToNearCode(); SetJumpTarget(c); - - gpr.UnlockAllX(); } void Jit64::dcbt(UGeckoInstruction inst) |