diff options
| author | Ryan Houdek <Sonicadvance1@Gmail.com> | 2013-09-16 15:44:41 +0000 |
|---|---|---|
| committer | Ryan Houdek <Sonicadvance1@Gmail.com> | 2013-09-16 15:44:41 +0000 |
| commit | 1529bb48c87bbe3af1d9aeeb2bd10cfe396dcd13 (patch) | |
| tree | 95fef8a7722c1378876f63adb083a3c739051c6b /Source/Core | |
| parent | 7397867b21883aa586ae627f7fc00e5f23160e21 (diff) | |
[ARM] Flush the fpr cache between every instruction. Do this until I figure out what is destroying the FPR register states.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp index 8b11840682..c7cdb81d21 100644 --- a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp +++ b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp @@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo BKPT(0x7777); } JitArmTables::CompileInstruction(ops[i]); + fpr.Flush(); if (js.memcheck && (opinfo->flags & FL_LOADSTORE)) { // Don't do this yet |