diff options
| author | XTra.KrazzY <XTra.KrazzY@gmail.com> | 2008-11-22 20:06:20 +0000 |
|---|---|---|
| committer | XTra.KrazzY <XTra.KrazzY@gmail.com> | 2008-11-22 20:06:20 +0000 |
| commit | 159e3f5b49ba2dc7eb0efb4a25a934d64ec71389 (patch) | |
| tree | 82631e995b102ac61897375bc8f25078398aab27 /Source/Core | |
| parent | 0a47860bcfaf4a90853dfe724ac766bff174290c (diff) | |
Fixed saving/loading states in OGL plugin.
Turns out the BPReload function is written plain wrong. Also, most chances are that the state will load correctly when not reloading the BP (not now though).
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1247 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Common/Src/ChunkFile.h | 4 | ||||
| -rw-r--r-- | Source/Core/Common/Src/x64Emitter.cpp | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/Source/Core/Common/Src/ChunkFile.h b/Source/Core/Common/Src/ChunkFile.h index 985504571f..96ffc21f02 100644 --- a/Source/Core/Common/Src/ChunkFile.h +++ b/Source/Core/Common/Src/ChunkFile.h @@ -48,8 +48,8 @@ public: enum Mode // also defined in pluginspecs.h. Didn't want to couple them.
{
MODE_READ = 1,
- MODE_WRITE = 2,
- MODE_MEASURE = 3,
+ MODE_WRITE,
+ MODE_MEASURE,
};
u8 **ptr;
diff --git a/Source/Core/Common/Src/x64Emitter.cpp b/Source/Core/Common/Src/x64Emitter.cpp index 1324cb7761..be525c8035 100644 --- a/Source/Core/Common/Src/x64Emitter.cpp +++ b/Source/Core/Common/Src/x64Emitter.cpp @@ -927,9 +927,10 @@ namespace Gen void AND (int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmAND, a1, a2);}
void OR (int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmOR , a1, a2);}
void XOR (int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmXOR, a1, a2);}
- void MOV (int bits, const OpArg &a1, const OpArg &a2)
+ inline void MOV (int bits, const OpArg &a1, const OpArg &a2)
{
- _assert_msg_(DYNA_REC, !a1.IsSimpleReg() || !a2.IsSimpleReg() || a1.GetSimpleReg() != a2.GetSimpleReg(), "Redundant MOV @ %p", code);
+ _assert_msg_(DYNA_REC, !a1.IsSimpleReg() || !a2.IsSimpleReg() || a1.GetSimpleReg() != a2.GetSimpleReg(), "Redundant MOV @ %p",
+ code);
WriteNormalOp(bits, nrmMOV, a1, a2);
}
void TEST(int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(bits, nrmTEST, a1, a2);}
|