diff options
| author | Ryan Houdek <Sonicadvance1@gmail.com> | 2013-09-12 23:07:19 -0500 |
|---|---|---|
| committer | Ryan Houdek <Sonicadvance1@gmail.com> | 2013-09-12 23:07:19 -0500 |
| commit | 1680f27739eeebeb7b48d91e8a4e3b80d7c75fe6 (patch) | |
| tree | 96b38f30e8f4dc58bb55420fd70770d8da543eff /Source/Core | |
| parent | ef1d33647f57553b7d0a2f0aed11c0b60a54ab4c (diff) | |
[ARM] Disable loadstorepaired instructions when fastmem is disabled.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp index 7ed402593c..bae9042dd0 100644 --- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp +++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp @@ -25,8 +25,7 @@ void JitArm::psq_l(UGeckoInstruction inst) // R12 contains scale // R11 contains type // R10 is the ADDR - - if (js.memcheck) { Default(inst); return; } + if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I])); UBFX(R12, R11, 16, 3); // Type @@ -66,8 +65,8 @@ void JitArm::psq_st(UGeckoInstruction inst) // R12 contains scale // R11 contains type // R10 is the ADDR - if (js.memcheck) { Default(inst); return; } - + if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } + LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I])); UBFX(R12, R11, 0, 3); // Type LSL(R12, R12, 2); |