diff options
| author | Mat M <mathew1800@gmail.com> | 2018-08-30 04:18:36 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-30 04:18:36 -0400 |
| commit | 3405c7d420cb909e00a3140ab2e31b911afe176c (patch) | |
| tree | 3b72d48f659f939dd51d173f2db4a3d81d2b9626 /Source/Core | |
| parent | 215d99146d72bc933a0cd190e87c8de03617044b (diff) | |
| parent | 9753f21cc74b329401577939e073353ca919b36b (diff) | |
Merge pull request #7386 from MerryMage/seq-points
Arm64Emitter: Remove unsequenced expressions
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.cpp | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index 2864b2fc38..957c3d4215 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -2137,13 +2137,23 @@ void ARM64XEmitter::ABI_PushRegisters(BitSet32 registers) // The first push must adjust the SP, else a context switch may invalidate everything below SP. if (num_regs & 1) + { STR(INDEX_PRE, (ARM64Reg)(X0 + *it++), SP, -stack_size); + } else - STP(INDEX_PRE, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, -stack_size); + { + ARM64Reg first_reg = (ARM64Reg)(X0 + *it++); + ARM64Reg second_reg = (ARM64Reg)(X0 + *it++); + STP(INDEX_PRE, first_reg, second_reg, SP, -stack_size); + } // Fast store for all other registers, this is always an even number. for (int i = 0; i < (num_regs - 1) / 2; i++) - STP(INDEX_SIGNED, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, 16 * (i + 1)); + { + ARM64Reg odd_reg = (ARM64Reg)(X0 + *it++); + ARM64Reg even_reg = (ARM64Reg)(X0 + *it++); + STP(INDEX_SIGNED, odd_reg, even_reg, SP, 16 * (i + 1)); + } ASSERT_MSG(DYNA_REC, it == registers.end(), "%s registers don't match.", __func__); } @@ -2168,7 +2178,11 @@ void ARM64XEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask) // Fast load for all but the first (two) registers, this is always an even number. for (int i = 0; i < (num_regs - 1) / 2; i++) - LDP(INDEX_SIGNED, (ARM64Reg)(X0 + *it++), (ARM64Reg)(X0 + *it++), SP, 16 * (i + 1)); + { + ARM64Reg odd_reg = (ARM64Reg)(X0 + *it++); + ARM64Reg even_reg = (ARM64Reg)(X0 + *it++); + LDP(INDEX_SIGNED, odd_reg, even_reg, SP, 16 * (i + 1)); + } // Post loading the first (two) registers. if (num_regs & 1) |