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authorRyan Houdek <Sonicadvance1@Gmail.com>2013-08-05 18:33:44 +0000
committerRyan Houdek <Sonicadvance1@Gmail.com>2013-08-05 18:33:51 +0000
commit4752eae677f27c8ebe86b0e1cb0f0df727efa3bc (patch)
treeabff29a47b055e5f6f36756155a66fad3d4eba40 /Source/Core
parent0d2083c670a0cf388aab689b39cd6954ebd183a8 (diff)
[ARM] Fix IMM support in the register cache.
Diffstat (limited to 'Source/Core')
-rw-r--r--Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp15
-rw-r--r--Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp12
-rw-r--r--Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.h2
3 files changed, 23 insertions, 6 deletions
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
index b05cbffbdd..17bacf175a 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -59,18 +59,23 @@ void JitArm::addi(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(Integer)
-
- ARMReg RD = gpr.R(inst.RD);
-
- if (inst.RA)
+ u32 d = inst.RD, a = inst.RA;
+ if (a)
{
+
+ if (gpr.IsImm(a) && gpr.IsImm(d))
+ {
+ gpr.SetImmediate(d, gpr.GetImm(d) + gpr.GetImm(a) + inst.SIMM_16);
+ return;
+ }
ARMReg rA = gpr.GetReg(false);
ARMReg RA = gpr.R(inst.RA);
+ ARMReg RD = gpr.R(inst.RD);
MOVI2R(rA, (u32)inst.SIMM_16);
ADD(RD, RA, rA);
}
else
- MOVI2R(RD, inst.SIMM_16);
+ gpr.SetImmediate(d, inst.SIMM_16);
}
void JitArm::addis(UGeckoInstruction inst)
{
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp
index 87fcb2dd76..be79bd4b71 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.cpp
@@ -194,6 +194,18 @@ ARMReg ArmRegCache::BindToRegister(u32 preg)
}
}
+void ArmRegCache::SetImmediate(u32 preg, u32 imm)
+{
+ if (regs[preg].GetType() == REG_REG)
+ {
+ // Dump real reg at this point
+ u32 regindex = regs[preg].GetRegIndex();
+ ArmCRegs[regindex].PPCReg = 33;
+ ArmCRegs[regindex].LastLoad = 0;
+ }
+ regs[preg].LoadToImm(imm);
+}
+
void ArmRegCache::Flush()
{
for (u8 a = 0; a < 32; ++a)
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.h b/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.h
index 5b8d0e04d0..82fa07b877 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.h
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitRegCache.h
@@ -134,7 +134,7 @@ public:
ARMReg R(u32 preg); // Returns a cached register
bool IsImm(u32 preg) { return regs[preg].GetType() == REG_IMM; }
u32 GetImm(u32 preg) { return regs[preg].GetImm(); }
- void SetImmediate(u32 preg, u32 imm) { regs[preg].LoadToImm(imm); }
+ void SetImmediate(u32 preg, u32 imm);
ARMReg BindToRegister(u32 preg);
};