diff options
| author | Fiora <fioraaeterna@gmail.com> | 2014-10-15 07:04:27 -0700 |
|---|---|---|
| committer | Fiora <fioraaeterna@gmail.com> | 2014-11-29 11:30:52 -0800 |
| commit | 4e0591cdf19607c9f4e2852fbb270d1cef2a422b (patch) | |
| tree | 7de834afa05e431ec8c78719ece64a5c5a375828 /Source/Core | |
| parent | 8d039a77aff143e938f063fee97263578246aa22 (diff) | |
JIT: float instruction attribute fixes, fix binding mistakes
These instructions modify only the bottom halves of the output register,
so the output register needs to be treated as an input too.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp | 10 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp | 12 |
2 files changed, 11 insertions, 11 deletions
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp index d34333761b..65d88872b4 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp @@ -321,14 +321,14 @@ static GekkoOPTemplate table59[] = static GekkoOPTemplate table63[] = { - {264, Interpreter::fabsx, {"fabsx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, + {264, Interpreter::fabsx, {"fabsx", OPTYPE_DOUBLEFP, FL_INOUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, {32, Interpreter::fcmpo, {"fcmpo", OPTYPE_DOUBLEFP, FL_IN_FLOAT_AB | FL_RC_BIT_F | FL_USE_FPU | FL_SET_FPRF, 1, 0, 0, 0}}, {0, Interpreter::fcmpu, {"fcmpu", OPTYPE_DOUBLEFP, FL_IN_FLOAT_AB | FL_RC_BIT_F | FL_USE_FPU | FL_SET_FPRF, 1, 0, 0, 0}}, - {14, Interpreter::fctiwx, {"fctiwx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, - {15, Interpreter::fctiwzx, {"fctiwzx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, + {14, Interpreter::fctiwx, {"fctiwx", OPTYPE_DOUBLEFP, FL_INOUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, + {15, Interpreter::fctiwzx, {"fctiwzx", OPTYPE_DOUBLEFP, FL_INOUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, {72, Interpreter::fmrx, {"fmrx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, - {136, Interpreter::fnabsx, {"fnabsx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, - {40, Interpreter::fnegx, {"fnegx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, + {136, Interpreter::fnabsx, {"fnabsx", OPTYPE_DOUBLEFP, FL_INOUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, + {40, Interpreter::fnegx, {"fnegx", OPTYPE_DOUBLEFP, FL_INOUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU, 1, 0, 0, 0}}, {12, Interpreter::frspx, {"frspx", OPTYPE_DOUBLEFP, FL_OUT_FLOAT_D | FL_IN_FLOAT_B | FL_RC_BIT_F | FL_USE_FPU | FL_SET_FPRF, 1, 0, 0, 0}}, {64, Interpreter::mcrfs, {"mcrfs", OPTYPE_SYSTEMFP, FL_SET_CRn | FL_USE_FPU | FL_READ_FPRF, 1, 0, 0, 0}}, diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp index 1c67ef8bed..84e1ce4969 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp @@ -152,7 +152,7 @@ void Jit64::fmaddXX(UGeckoInstruction inst) PXOR(XMM0, M((void*)&psSignBits)); } - fpr.BindToRegister(d, false); + fpr.BindToRegister(d, !single); //YES it is necessary to dupe the result :( //TODO : analysis - does the top reg get used? If so, dupe, if not, don't. if (single) @@ -177,7 +177,7 @@ void Jit64::fsign(UGeckoInstruction inst) int d = inst.FD; int b = inst.FB; fpr.Lock(b, d); - fpr.BindToRegister(d, true, true); + fpr.BindToRegister(d); if (d != b) MOVSD(fpr.RX(d), fpr.R(b)); @@ -231,7 +231,7 @@ void Jit64::fselx(UGeckoInstruction inst) PANDN(XMM1, fpr.R(c)); POR(XMM1, R(XMM0)); } - fpr.BindToRegister(d, true); + fpr.BindToRegister(d); MOVSD(fpr.RX(d), R(XMM1)); fpr.UnlockAll(); } @@ -384,7 +384,7 @@ void Jit64::fctiwx(UGeckoInstruction inst) int d = inst.RD; int b = inst.RB; fpr.Lock(d, b); - fpr.BindToRegister(d, d == b); + fpr.BindToRegister(d); // Intel uses 0x80000000 as a generic error code while PowerPC uses clamping: // @@ -443,7 +443,7 @@ void Jit64::frsqrtex(UGeckoInstruction inst) gpr.FlushLockX(RSCRATCH_EXTRA); fpr.Lock(b, d); - fpr.BindToRegister(d, d == b); + fpr.BindToRegister(d); MOVAPD(XMM0, fpr.R(b)); CALL((void *)asm_routines.frsqrte); MOVSD(fpr.R(d), XMM0); @@ -462,7 +462,7 @@ void Jit64::fresx(UGeckoInstruction inst) gpr.FlushLockX(RSCRATCH_EXTRA); fpr.Lock(b, d); - fpr.BindToRegister(d, d == b); + fpr.BindToRegister(d); MOVAPD(XMM0, fpr.R(b)); CALL((void *)asm_routines.fres); MOVSD(fpr.R(d), XMM0); |
