[ARM] Implement andx, andi_rc, and andis_rc.

3 files changed, 68 insertions, 3 deletions

diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
index a32b1df494..54df2052f0 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.h
@@ -154,6 +154,9 @@ public:
 	void oris(UGeckoInstruction _inst);	
 	void orx(UGeckoInstruction _inst);
 	void xorx(UGeckoInstruction _inst);
+	void andx(UGeckoInstruction _inst);
+	void andi_rc(UGeckoInstruction _inst);
+	void andis_rc(UGeckoInstruction _inst);
 	void rlwimix(UGeckoInstruction _inst);
 	void rlwinmx(UGeckoInstruction _inst);
 	void subfx(UGeckoInstruction _inst);
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
index b109882196..0e5249d4ce 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Integer.cpp
@@ -246,6 +246,68 @@ void JitArm::xorx(UGeckoInstruction inst)
 	if (inst.Rc)
 		ComputeRC();
 }
+
+void JitArm::andx(UGeckoInstruction inst)
+{
+	u32 a = inst.RA, b = inst.RB, s = inst.RS;
+
+	if (gpr.IsImm(s) && gpr.IsImm(b))
+	{
+		gpr.SetImmediate(a, gpr.GetImm(s) & gpr.GetImm(b));
+		if (inst.Rc) ComputeRC(gpr.GetImm(a), 0); 
+		return;
+	}
+	ARMReg rA = gpr.R(a);
+	ARMReg rB = gpr.R(b);
+	ARMReg rS = gpr.R(s);
+
+	ANDS(rA, rS, rB);
+
+	if (inst.Rc) ComputeRC();
+}
+
+void JitArm::andi_rc(UGeckoInstruction inst)
+{
+	u32 a = inst.RA, s = inst.RS;
+
+	if (gpr.IsImm(s))
+	{
+		gpr.SetImmediate(a, gpr.GetImm(s) & inst.UIMM);
+		ComputeRC(gpr.GetImm(a), 0); 
+		return;
+	}
+	ARMReg rA = gpr.R(a);
+	ARMReg rS = gpr.R(s);
+	ARMReg RA = gpr.GetReg();
+
+	MOVI2R(RA, inst.UIMM);
+	ANDS(rA, rS, RA);
+
+	ComputeRC();
+	gpr.Unlock(RA);
+}
+
+void JitArm::andis_rc(UGeckoInstruction inst)
+{
+	u32 a = inst.RA, s = inst.RS;
+
+	if (gpr.IsImm(s))
+	{
+		gpr.SetImmediate(a, gpr.GetImm(s) & ((u32)inst.UIMM << 16));
+		ComputeRC(gpr.GetImm(a), 0); 
+		return;
+	}
+	ARMReg rA = gpr.R(a);
+	ARMReg rS = gpr.R(s);
+	ARMReg RA = gpr.GetReg();
+
+	MOVI2R(RA, (u32)inst.UIMM << 16);
+	ANDS(rA, rS, RA);
+
+	ComputeRC();
+	gpr.Unlock(RA);
+}
+
 void JitArm::extshx(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
index 570bde105c..2557b2de9c 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_Tables.cpp
@@ -75,8 +75,8 @@ static GekkoOPTemplate primarytable[] =
 	{25, &JitArm::oris}, //"oris",     OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
 	{26, &JitArm::Default}, //"xori",     OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
 	{27, &JitArm::Default}, //"xoris",    OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
-	{28, &JitArm::Default}, //"andi_rc",  OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
-	{29, &JitArm::Default}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
+	{28, &JitArm::andi_rc}, //"andi_rc",  OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
+	{29, &JitArm::andis_rc}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
 
 	{32, &JitArm::lwz}, //"lwz",  OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
 	{33, &JitArm::Default}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
@@ -194,7 +194,7 @@ static GekkoOPTemplate table19[] =
 
 static GekkoOPTemplate table31[] = 
 {
-	{28,  &JitArm::Default}, //"andx",   OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
+	{28,  &JitArm::andx}, //"andx",   OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
 	{60,  &JitArm::Default}, //"andcx",  OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
 	{444, &JitArm::orx}, //"orx",    OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
 	{124, &JitArm::Default}, //"norx",   OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},