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authorPokechu22 <Pokechu022@gmail.com>2022-07-22 15:07:19 -0700
committerPokechu22 <Pokechu022@gmail.com>2022-07-22 22:22:34 -0700
commit5bbdf7ae154a5da03d66c38855f2b1890a2a3dc8 (patch)
treeb0f50c50ab54002c896944cca2763328d65f8453 /Source/Core
parent97412553f9e888f4bd8c4f01c240437fca696eab (diff)
ProcessorInterface: Reset both GPFifo and Fifo on PI_FIFO_RESET
Fixes https://bugs.dolphin-emu.org/issues/12981
Diffstat (limited to 'Source/Core')
-rw-r--r--Source/Core/Core/HW/ProcessorInterface.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/Source/Core/Core/HW/ProcessorInterface.cpp b/Source/Core/Core/HW/ProcessorInterface.cpp
index bc0321c2dd..5e752c13f7 100644
--- a/Source/Core/Core/HW/ProcessorInterface.cpp
+++ b/Source/Core/Core/HW/ProcessorInterface.cpp
@@ -106,7 +106,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
// Used by GXAbortFrame
INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_FIFO_RESET: {:08x}", val);
if ((val & 1) != 0)
+ {
+ GPFifo::ResetGatherPipe();
Fifo::ResetVideoBuffer();
+ }
}));
mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](u32) {