diff options
| author | pierre <pierre@pirsoft.de> | 2010-10-14 13:17:38 +0000 |
|---|---|---|
| committer | pierre <pierre@pirsoft.de> | 2010-10-14 13:17:38 +0000 |
| commit | 6d2c35a332e06c31bdbfdb2eabe147e8e947d9b2 (patch) | |
| tree | 518dc7833d486eecfe12c7ca89a7b7c38b090eb3 /Source/Core | |
| parent | 47eb5c3416780007318247757a688528df5141ea (diff) | |
Core/DSPCore: Jit: only end emitting the current block when hitting an
unconditional branch(or idle skip), emit check g_dsp.pc and return when
hitting a conditional branch.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6281 8ced0084-cf51-0410-be5f-012b33b47a6e
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/DSPCore/Src/DSPEmitter.cpp | 29 | ||||
| -rw-r--r-- | Source/Core/DSPCore/Src/DSPTables.cpp | 468 | ||||
| -rw-r--r-- | Source/Core/DSPCore/Src/DSPTables.h | 1 |
3 files changed, 260 insertions, 238 deletions
diff --git a/Source/Core/DSPCore/Src/DSPEmitter.cpp b/Source/Core/DSPCore/Src/DSPEmitter.cpp index 8347852c48..7b0a27c362 100644 --- a/Source/Core/DSPCore/Src/DSPEmitter.cpp +++ b/Source/Core/DSPCore/Src/DSPEmitter.cpp @@ -225,10 +225,31 @@ const u8 *DSPEmitter::Compile(int start_addr) { SetJumpTarget(rLoopCounterExit); } - // End the block if we're at a loop end. - if (opcode->branch || - (DSPAnalyzer::code_flags[addr-1] & DSPAnalyzer::CODE_LOOP_END) || - (DSPAnalyzer::code_flags[addr] & DSPAnalyzer::CODE_IDLE_SKIP)) { + if (opcode->branch) { + if (opcode->uncond_branch) { + break; + } else { + //look at g_dsp.pc if we actually branched +#ifdef _M_IX86 // All32 + MOV(16, R(AX), M(&(g_dsp.pc))); +#else + MOV(64, R(RAX), ImmPtr(&(g_dsp.pc))); + MOV(16, R(AX), MDisp(RAX,0)); +#endif + CMP(16, R(AX), Imm16(addr)); + FixupBranch rNoBranch = J_CC(CC_Z); + + // ABI_RestoreStack(0); + ABI_PopAllCalleeSavedRegsAndAdjustStack(); + MOV(32,R(EAX),Imm32(blockSize[start_addr])); + RET(); + + SetJumpTarget(rNoBranch); + } + } + + // End the block if we're before an idle skip address + if (DSPAnalyzer::code_flags[addr] & DSPAnalyzer::CODE_IDLE_SKIP) { break; } } diff --git a/Source/Core/DSPCore/Src/DSPTables.cpp b/Source/Core/DSPCore/Src/DSPTables.cpp index 486ac7e6d0..e154667006 100644 --- a/Source/Core/DSPCore/Src/DSPTables.cpp +++ b/Source/Core/DSPCore/Src/DSPTables.cpp @@ -33,270 +33,270 @@ void nop(const UDSPInstruction opc) const DSPOPCTemplate opcodes[] = { - {"NOP", 0x0000, 0xfffc, nop, &DSPEmitter::nop, 1, 0, {}, false, false}, - - {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, &DSPEmitter::dar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, - {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, &DSPEmitter::iar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, - {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, &DSPEmitter::subarn, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false}, - {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, &DSPEmitter::addarn, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false}, - - {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, NULL, 1, 0, {}, false, true}, - - {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RETO", 0x02de, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - {"RET", 0x02df, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true}, - - {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, NULL, 1, 0, {}, false, true}, - - {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALLO", 0x02be, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - - {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - {"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true}, - - {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JO", 0x029e, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - - {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - - {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRLNZ",0x171c, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true}, - - {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false}, - {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false}, - - {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, - {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, - {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, - {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false}, - - {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, NULL, 1, 0, {}, false, false}, // discovered by ector! - {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, NULL, 1, 0, {}, false, false}, // discovered by ector! - - {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false}, - {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, NULL, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - - {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, NULL, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - - {"SI", 0x1600, 0xff00, DSPInterpreter::si, NULL, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - - {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, - {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, - {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false}, - - {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - - {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false}, - - {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, - {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, - {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, - {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false}, + {"NOP", 0x0000, 0xfffc, nop, &DSPEmitter::nop, 1, 0, {}, false, false, false}, + + {"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, &DSPEmitter::dar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false}, + {"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, &DSPEmitter::iar, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false}, + {"SUBARN", 0x000c, 0xfffc, DSPInterpreter::subarn, &DSPEmitter::subarn, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false}, + {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, &DSPEmitter::addarn, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false}, + + {"HALT", 0x0021, 0xffff, DSPInterpreter::halt, NULL, 1, 0, {}, false, true, true}, + + {"RETGE", 0x02d0, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETL", 0x02d1, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETG", 0x02d2, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETLE", 0x02d3, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETNZ", 0x02d4, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETZ", 0x02d5, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETNC", 0x02d6, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETC", 0x02d7, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETx8", 0x02d8, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETx9", 0x02d9, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETxA", 0x02da, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETxB", 0x02db, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETLNZ", 0x02dc, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETLZ", 0x02dd, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RETO", 0x02de, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, false}, + {"RET", 0x02df, 0xffff, DSPInterpreter::ret, NULL, 1, 0, {}, false, true, true}, + + {"RTI", 0x02ff, 0xffff, DSPInterpreter::rti, NULL, 1, 0, {}, false, true, true}, + + {"CALLGE", 0x02b0, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLL", 0x02b1, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLG", 0x02b2, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLLE", 0x02b3, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLNZ", 0x02b4, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLZ", 0x02b5, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLNC", 0x02b6, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLC", 0x02b7, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLx8", 0x02b8, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLx9", 0x02b9, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLxA", 0x02ba, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLxB", 0x02bb, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLLNZ", 0x02bc, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLLZ", 0x02bd, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALLO", 0x02be, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"CALL", 0x02bf, 0xffff, DSPInterpreter::call, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true}, + + {"IFGE", 0x0270, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFL", 0x0271, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFG", 0x0272, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFLE", 0x0273, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFNZ", 0x0274, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFZ", 0x0275, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFNC", 0x0276, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFC", 0x0277, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFx8", 0x0278, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFx9", 0x0279, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFxA", 0x027a, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFxB", 0x027b, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFLNZ", 0x027c, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFLZ", 0x027d, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IFO", 0x027e, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, false}, + {"IF", 0x027f, 0xffff, DSPInterpreter::ifcc, NULL, 1, 0, {}, false, true, true}, + + {"JGE", 0x0290, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JL", 0x0291, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JG", 0x0292, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JLE", 0x0293, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JNZ", 0x0294, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JZ", 0x0295, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JNC", 0x0296, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JC", 0x0297, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JMPx8", 0x0298, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JMPx9", 0x0299, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JMPxA", 0x029a, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JMPxB", 0x029b, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JLNZ", 0x029c, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JO", 0x029e, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, NULL, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true}, + + {"JRGE", 0x1700, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRL", 0x1701, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRG", 0x1702, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRLE", 0x1703, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRNZ", 0x1704, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRZ", 0x1705, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRNC", 0x1706, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRC", 0x1707, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JMPRx8", 0x1708, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JMPRx9", 0x1709, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JMPRxA", 0x170a, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JMPRxB", 0x170b, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRLNZ", 0x170c, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRLZ", 0x170d, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JRO", 0x170e, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"JMPR", 0x170f, 0xff1f, DSPInterpreter::jmprcc, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true}, + + {"CALLRGE", 0x1710, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRL", 0x1711, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRG", 0x1712, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRLE", 0x1713, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRNZ", 0x1714, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRZ", 0x1715, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRNC", 0x1716, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRC", 0x1717, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRx8", 0x1718, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRx9", 0x1719, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRxA", 0x171a, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRxB", 0x171b, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRLNZ", 0x171c, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRLZ", 0x171d, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLRO", 0x171e, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false}, + {"CALLR", 0x171f, 0xff1f, DSPInterpreter::callr, NULL, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true}, + + {"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false}, + {"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false}, + + {"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false}, + {"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false}, + {"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false}, + {"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false}, + + {"LSRN", 0x02ca, 0xffff, DSPInterpreter::lsrn, NULL, 1, 0, {}, false, false, false}, // discovered by ector! + {"ASRN", 0x02cb, 0xffff, DSPInterpreter::asrn, NULL, 1, 0, {}, false, false, false}, // discovered by ector! + + {"LRI", 0x0080, 0xffe0, DSPInterpreter::lri, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"LR", 0x00c0, 0xffe0, DSPInterpreter::lr, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false}, + {"SR", 0x00e0, 0xffe0, DSPInterpreter::sr, NULL, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, + + {"MRR", 0x1c00, 0xfc00, DSPInterpreter::mrr, NULL, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, + + {"SI", 0x1600, 0xff00, DSPInterpreter::si, NULL, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + + {"ADDIS", 0x0400, 0xfe00, DSPInterpreter::addis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false}, + {"CMPIS", 0x0600, 0xfe00, DSPInterpreter::cmpis, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false}, + {"LRIS", 0x0800, 0xf800, DSPInterpreter::lris, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false}, + + {"ADDI", 0x0200, 0xfeff, DSPInterpreter::addi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"XORI", 0x0220, 0xfeff, DSPInterpreter::xori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"ANDI", 0x0240, 0xfeff, DSPInterpreter::andi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"ORI", 0x0260, 0xfeff, DSPInterpreter::ori, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"CMPI", 0x0280, 0xfeff, DSPInterpreter::cmpi, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + + {"ANDF", 0x02a0, 0xfeff, DSPInterpreter::andf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + {"ANDCF", 0x02c0, 0xfeff, DSPInterpreter::andcf, NULL, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false}, + + {"ILRR", 0x0210, 0xfefc, DSPInterpreter::ilrr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false}, + {"ILRRD", 0x0214, 0xfefc, DSPInterpreter::ilrrd, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false}, + {"ILRRI", 0x0218, 0xfefc, DSPInterpreter::ilrri, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false}, + {"ILRRN", 0x021c, 0xfefc, DSPInterpreter::ilrrn, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false}, // LOOPS - {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true}, - {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, - {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true}, - {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true}, + {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, NULL, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, false}, + {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, NULL, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, + {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, NULL, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, false}, + {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, NULL, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false}, // load and store value pointed by indexing reg and increment; LRR/SRR variants - {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, - {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, - {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, - {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false}, + {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false}, + {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false}, + {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false}, + {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, NULL, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false}, - {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, - {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false}, + {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, + {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, + {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, + {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, NULL, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false}, //2 - {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false}, - {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, NULL, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false}, + {"LRS", 0x2000, 0xf800, DSPInterpreter::lrs, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false}, + {"SRS", 0x2800, 0xf800, DSPInterpreter::srs, NULL, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false}, // opcodes that can be extended //3 - main opcode defined by 9 bits, extension defined by last 7 bits!! - {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, - {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, - {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, - {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, - {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, - {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, NULL, 1 , 2, {{P_ACCM, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, - {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, - {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, - {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_REG1A, 1, 0, 9, 0x0200}}, true, false}, - {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, - {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100},{P_ACCM_D, 1, 0, 8, 0x0100}}, true, false}, + {"XORR", 0x3000, 0xfc80, DSPInterpreter::xorr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false}, + {"ANDR", 0x3400, 0xfc80, DSPInterpreter::andr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false}, + {"ORR", 0x3800, 0xfc80, DSPInterpreter::orr, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false}, + {"ANDC", 0x3c00, 0xfe80, DSPInterpreter::andc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"ORC", 0x3e00, 0xfe80, DSPInterpreter::orc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"XORC", 0x3080, 0xfe80, DSPInterpreter::xorc, NULL, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"NOT", 0x3280, 0xfe80, DSPInterpreter::notc, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false}, + {"LSRNRX", 0x3480, 0xfc80, DSPInterpreter::lsrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false}, + {"ASRNRX", 0x3880, 0xfc80, DSPInterpreter::asrnrx, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false}, + {"LSRNR", 0x3c80, 0xfe80, DSPInterpreter::lsrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false}, //4 - {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, - {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, - {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, - {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false}, + {"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false}, + {"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, //5 - {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, - {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, - {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, - {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"SUBR", 0x5000, 0xf800, DSPInterpreter::subr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false}, + {"SUBAX", 0x5800, 0xfc00, DSPInterpreter::subax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false}, + {"SUB", 0x5c00, 0xfe00, DSPInterpreter::sub, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"SUBP", 0x5e00, 0xfe00, DSPInterpreter::subp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, //6 - {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false}, - {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false}, - {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false}, - {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MOVR", 0x6000, 0xf800, DSPInterpreter::movr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false}, + {"MOVAX", 0x6800, 0xfc00, DSPInterpreter::movax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false}, + {"MOV", 0x6c00, 0xfe00, DSPInterpreter::mov, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false}, + {"MOVP", 0x6e00, 0xfe00, DSPInterpreter::movp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, //7 - {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, NULL, 1 , 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false}, - {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, - {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, NULL, 1 , 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false}, - {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"ADDAXL", 0x7000, 0xfc00, DSPInterpreter::addaxl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false}, + {"INCM", 0x7400, 0xfe00, DSPInterpreter::incm, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false}, + {"INC", 0x7600, 0xfe00, DSPInterpreter::inc, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"DECM", 0x7800, 0xfe00, DSPInterpreter::decm, NULL, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false}, + {"DEC", 0x7a00, 0xfe00, DSPInterpreter::dec, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"NEG", 0x7c00, 0xfe00, DSPInterpreter::neg, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MOVNP", 0x7e00, 0xfe00, DSPInterpreter::movnp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, //8 - {"NX", 0x8000, 0xf700, DSPInterpreter::nx, NULL, 1 , 0, {}, true, false}, - {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, - {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, NULL, 1 , 0, {}, true, false}, - {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, NULL, 1 , 0, {}, true, false}, - {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, NULL, 1 , 0, {}, true, false}, - {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, NULL, 1 , 0, {}, true, false}, - {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, NULL, 1 , 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false}, - {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, - {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, - {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, - {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, - {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, - {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1 , 0, {}, true, false}, + {"NX", 0x8000, 0xf700, DSPInterpreter::nx, NULL, 1, 0, {}, true, false, false}, + {"CLR", 0x8100, 0xf700, DSPInterpreter::clr, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false}, + {"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, NULL, 1, 0, {}, true, false, false}, + {"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, NULL, 1, 0, {}, true, false, false}, + {"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, NULL, 1, 0, {}, true, false, false}, + {"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, NULL, 1, 0, {}, true, false, false}, + {"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, NULL, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false}, + {"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, + {"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, + {"CLR15", 0x8c00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, + {"SET15", 0x8d00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, + {"SET16", 0x8e00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, + {"SET40", 0x8f00, 0xff00, DSPInterpreter::srbith, &DSPEmitter::srbith, 1, 0, {}, true, false, false}, //9 - {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, NULL, 1 , 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, - {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, - {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, NULL, 1 , 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - + {"MUL", 0x9000, 0xf700, DSPInterpreter::mul, NULL, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false}, + {"ASR16", 0x9100, 0xf700, DSPInterpreter::asr16, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false}, + {"MULMVZ", 0x9200, 0xf600, DSPInterpreter::mulmvz, NULL, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULAC", 0x9400, 0xf600, DSPInterpreter::mulac, NULL, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULMV", 0x9600, 0xf600, DSPInterpreter::mulmv, NULL, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + //a-b - {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, NULL, 1 , 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false}, - {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, - {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, NULL, 1 , 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"TST", 0xb100, 0xf700, DSPInterpreter::tst, NULL, 1 , 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false}, + {"MULX", 0xa000, 0xe700, DSPInterpreter::mulx, NULL, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false}, + {"ABS", 0xa100, 0xf700, DSPInterpreter::abs, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false}, + {"MULXMVZ", 0xa200, 0xe600, DSPInterpreter::mulxmvz, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULXAC", 0xa400, 0xe600, DSPInterpreter::mulxac, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULXMV", 0xa600, 0xe600, DSPInterpreter::mulxmv, NULL, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"TST", 0xb100, 0xf700, DSPInterpreter::tst, NULL, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false}, //c-d - {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, NULL, 1 , 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, - {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, NULL, 1 , 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false}, - {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, NULL, 1 , 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"MULC", 0xc000, 0xe700, DSPInterpreter::mulc, NULL, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false}, + {"CMPAR" , 0xc100, 0xe700, DSPInterpreter::cmpar, NULL, 1, 2, {{P_ACC, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false}, + {"MULCMVZ", 0xc200, 0xe600, DSPInterpreter::mulcmvz, NULL, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULCAC", 0xc400, 0xe600, DSPInterpreter::mulcac, NULL, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MULCMV", 0xc600, 0xe600, DSPInterpreter::mulcmv, NULL, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, //e - {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, NULL, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false}, - {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, NULL, 1 , 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false}, - {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, NULL, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false}, - {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, NULL, 1 , 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false}, + {"MADDX", 0xe000, 0xfc00, DSPInterpreter::maddx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false}, + {"MSUBX", 0xe400, 0xfc00, DSPInterpreter::msubx, NULL, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false}, + {"MADDC", 0xe800, 0xfc00, DSPInterpreter::maddc, NULL, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false}, + {"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, NULL, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false}, //f - {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, NULL, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false}, - {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, - {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub , NULL, 1 , 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false}, - {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, NULL, 1 , 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false}, - {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, NULL, 1 , 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false}, - {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, NULL, 1 , 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false}, + {"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false}, + {"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, + {"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub, NULL, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false}, + {"ADDPAXZ", 0xf800, 0xfc00, DSPInterpreter::addpaxz, NULL, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false}, + {"CLRL", 0xfc00, 0xfe00, DSPInterpreter::clrl, NULL, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false}, + {"MOVPZ", 0xfe00, 0xfe00, DSPInterpreter::movpz, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false}, }; const DSPOPCTemplate cw = diff --git a/Source/Core/DSPCore/Src/DSPTables.h b/Source/Core/DSPCore/Src/DSPTables.h index 06bfcaa519..e1a86f4818 100644 --- a/Source/Core/DSPCore/Src/DSPTables.h +++ b/Source/Core/DSPCore/Src/DSPTables.h @@ -95,6 +95,7 @@ typedef struct param2_t params[8]; bool extended; bool branch; + bool uncond_branch; } DSPOPCTemplate; typedef DSPOPCTemplate opc_t; |