Merge pull request #8755 from Sintendo/jit64intopts

Jit64: More addx and subfx optimizations

1 files changed, 40 insertions, 10 deletions

diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
index 494969b71f..99b66d83fe 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
@@ -932,6 +932,10 @@ void Jit64::subfx(UGeckoInstruction inst)
       MOV(32, Rd, Rb);
       SUB(32, Rd, R(RSCRATCH));
     }
+    else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
+    {
+      LEA(32, Rd, MDisp(Rb.GetSimpleReg(), -Ra.SImm32()));
+    }
     else
     {
       MOV(32, Rd, Rb);
@@ -1330,25 +1334,51 @@ void Jit64::addx(UGeckoInstruction inst)
     RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
     RegCache::Realize(Ra, Rb, Rd);
 
-    if (d == a)
+    if ((d == a) || (d == b))
     {
-      ADD(32, Rd, Rb);
-    }
-    else if (d == b)
-    {
-      ADD(32, Rd, Ra);
+      RCOpArg& Rnotd = (d == a) ? Rb : Ra;
+      if (!Rnotd.IsZero() || inst.OE)
+      {
+        ADD(32, Rd, Rnotd);
+      }
     }
     else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
     {
       LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
     }
-    else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
+    else if ((Ra.IsSimpleReg() || Rb.IsSimpleReg()) && (Ra.IsImm() || Rb.IsImm()) && !inst.OE)
     {
-      LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
+      RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
+      RCOpArg& Rreg = Ra.IsImm() ? Rb : Ra;
+
+      if (Rimm.IsZero())
+      {
+        MOV(32, Rd, Rreg);
+      }
+      else
+      {
+        LEA(32, Rd, MDisp(Rreg.GetSimpleReg(), Rimm.SImm32()));
+      }
     }
-    else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
+    else if (Ra.IsImm() || Rb.IsImm())
     {
-      LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
+      RCOpArg& Rimm = Ra.IsImm() ? Ra : Rb;
+      RCOpArg& Rother = Ra.IsImm() ? Rb : Ra;
+
+      s32 imm = Rimm.SImm32();
+      if (imm >= -128 && imm <= 127)
+      {
+        MOV(32, Rd, Rother);
+        if (imm != 0 || inst.OE)
+        {
+          ADD(32, Rd, Rimm);
+        }
+      }
+      else
+      {
+        MOV(32, Rd, Rimm);
+        ADD(32, Rd, Rother);
+      }
     }
     else
     {