diff options
| author | Sintendo <bram.speeckaert@gmail.com> | 2020-04-19 22:38:58 +0200 |
|---|---|---|
| committer | Sintendo <bram.speeckaert@gmail.com> | 2020-04-21 22:06:39 +0200 |
| commit | 72fbdf1a6bafe8a01c58deae79fbae44535a34f4 (patch) | |
| tree | 190361919e1b38dc13d54dd6370cd3a77f0bccf3 /Source/Core | |
| parent | c33565295dd913991a543147f81be8687f3be737 (diff) | |
Jit64: addx - Deduplicate branches part 1
No functional change, just simplify some repeated logic for the cases
where the destination register matches one of the sources.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index 494969b71f..445f536d11 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -1330,13 +1330,10 @@ void Jit64::addx(UGeckoInstruction inst) RCX64Reg Rd = gpr.Bind(d, RCMode::Write); RegCache::Realize(Ra, Rb, Rd); - if (d == a) - { - ADD(32, Rd, Rb); - } - else if (d == b) + if ((d == a) || (d == b)) { - ADD(32, Rd, Ra); + RCOpArg& Rnotd = (d == a) ? Rb : Ra; + ADD(32, Rd, Rnotd); } else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE) { |