diff options
| author | Admiral H. Curtiss <pikachu025@gmail.com> | 2023-01-09 21:03:19 +0100 |
|---|---|---|
| committer | Admiral H. Curtiss <pikachu025@gmail.com> | 2023-01-27 15:22:41 +0100 |
| commit | 82f317087656382b855fec07df16f8d217e6fee4 (patch) | |
| tree | 68d191ed6acf6d9e3a2da416af56164806631346 /Source/Core | |
| parent | 8bab3ac755d4b89f294716d6d21ee6de5fe866bd (diff) | |
PowerPC: Parametrize THRM1/2/3 macros.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp | 6 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/PowerPC.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index 0316b3de81..d7ec9b3d1b 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -486,7 +486,7 @@ void Interpreter::mtspr(UGeckoInstruction inst) constexpr u32 SIMULATED_TEMP = 42; // °C auto UpdateThermalReg = [](UReg_THRM12* reg) { - if (!THRM3.E || !reg->V) + if (!THRM3(PowerPC::ppcState).E || !reg->V) { reg->TIV = 0; } @@ -500,8 +500,8 @@ void Interpreter::mtspr(UGeckoInstruction inst) } }; - UpdateThermalReg(&THRM1); - UpdateThermalReg(&THRM2); + UpdateThermalReg(&THRM1(PowerPC::ppcState)); + UpdateThermalReg(&THRM2(PowerPC::ppcState)); break; } } diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h index f086576549..072fcd0abc 100644 --- a/Source/Core/Core/PowerPC/PowerPC.h +++ b/Source/Core/Core/PowerPC/PowerPC.h @@ -242,9 +242,9 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst); #define DMAL(ppc_state) (*(UReg_DMAL*)&(ppc_state).spr[SPR_DMAL]) #define MMCR0(ppc_state) ((UReg_MMCR0&)(ppc_state).spr[SPR_MMCR0]) #define MMCR1(ppc_state) ((UReg_MMCR1&)(ppc_state).spr[SPR_MMCR1]) -#define THRM1 ((UReg_THRM12&)PowerPC::ppcState.spr[SPR_THRM1]) -#define THRM2 ((UReg_THRM12&)PowerPC::ppcState.spr[SPR_THRM2]) -#define THRM3 ((UReg_THRM3&)PowerPC::ppcState.spr[SPR_THRM3]) +#define THRM1(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM1]) +#define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2]) +#define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3]) #define PC PowerPC::ppcState.pc #define NPC PowerPC::ppcState.npc #define FPSCR PowerPC::ppcState.fpscr |