diff options
| author | JosJuice <josjuice@gmail.com> | 2025-08-24 09:40:26 +0200 |
|---|---|---|
| committer | JosJuice <josjuice@gmail.com> | 2026-01-18 20:02:49 +0100 |
| commit | 84261cfc2333e5ca94aedb79ef46768edf71d759 (patch) | |
| tree | 1807389a1ce879bb934cecb7e624a152e5e4ee9d /Source/Core | |
| parent | ff82ae3b5c443c1b1ffadc3789f98a6a758bb45b (diff) | |
Arm64Emitter: Fix Q bit of vector SHL/URSHR encoding
This doesn't affect any existing callers, because all existing callers
use quad registers.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Common/Arm64Emitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Source/Core/Common/Arm64Emitter.cpp b/Source/Core/Common/Arm64Emitter.cpp index d78257cf4f..70c808a81b 100644 --- a/Source/Core/Common/Arm64Emitter.cpp +++ b/Source/Core/Common/Arm64Emitter.cpp @@ -3664,7 +3664,7 @@ void ARM64FloatEmitter::SHL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift) { ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}", shift, src_size); - EmitShiftImm(1, 0, src_size | shift, 0b01010, Rd, Rn); + EmitShiftImm(IsQuad(Rd), 0, src_size | shift, 0b01010, Rd, Rn); } void ARM64FloatEmitter::SSHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper) @@ -3678,7 +3678,7 @@ void ARM64FloatEmitter::URSHR(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift) { ASSERT_MSG(DYNA_REC, shift < src_size, "Shift amount must be less than the element size! {} {}", shift, src_size); - EmitShiftImm(1, 1, src_size * 2 - shift, 0b00100, Rd, Rn); + EmitShiftImm(IsQuad(Rd), 1, src_size * 2 - shift, 0b00100, Rd, Rn); } void ARM64FloatEmitter::USHLL(u8 src_size, ARM64Reg Rd, ARM64Reg Rn, u32 shift, bool upper) |