diff options
| author | JosJuice <josjuice@gmail.com> | 2021-06-24 11:47:42 +0200 |
|---|---|---|
| committer | JosJuice <josjuice@gmail.com> | 2021-06-24 12:00:58 +0200 |
| commit | 8cd37e040adb5fa6d7491839bcd55bc085a594e7 (patch) | |
| tree | ba9143af813a6410cc768901084da5f580e60c2e /Source/Core | |
| parent | c77a5f7e3246398aeb1d520d7bbc0bfdf5787754 (diff) | |
JitArm64: Implement mffsx
Part 2 of implementing the FPSCR system register instructions.
Diffstat (limited to 'Source/Core')
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/Jit.h | 1 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp | 32 | ||||
| -rw-r--r-- | Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp | 2 |
3 files changed, 34 insertions, 1 deletions
diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h index c9f6d60919..7d1b026d30 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.h +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h @@ -119,6 +119,7 @@ public: void mfcr(UGeckoInstruction inst); void mtcrf(UGeckoInstruction inst); void mcrfs(UGeckoInstruction inst); + void mffsx(UGeckoInstruction inst); // LoadStore void lXX(UGeckoInstruction inst); diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp index 668e7fce26..a6d9682df5 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp @@ -721,3 +721,35 @@ void JitArm64::mcrfs(UGeckoInstruction inst) gpr.Unlock(WA); } + +void JitArm64::mffsx(UGeckoInstruction inst) +{ + INSTRUCTION_START + JITDISABLE(bJITSystemRegistersOff); + FALLBACK_IF(inst.Rc); + + ARM64Reg WA = gpr.GetReg(); + ARM64Reg XA = EncodeRegTo64(WA); + + LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr)); + + ARM64Reg VD = fpr.RW(inst.FD, RegType::LowerPair); + ARM64Reg WB = gpr.GetReg(); + + // FPSCR.FEX = 0; + // FPSCR.VX = (FPSCR.Hex & FPSCR_VX_ANY) != 0; + // (FEX is right next to VX, so we can set both using one BFI instruction) + MOVI2R(WB, FPSCR_VX_ANY); + TST(WA, WB); + CSET(WB, CCFlags::CC_NEQ); + BFI(WA, WB, 31 - 2, 2); + + STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr)); + + // Vd = FPSCR.Hex | 0xFFF8'0000'0000'0000; + ORR(XA, XA, 13, 12, true); + m_float_emit.FMOV(EncodeRegToDouble(VD), XA); + + gpr.Unlock(WA); + gpr.Unlock(WB); +} diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp index a3b5cce8c9..ad776ed31b 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp @@ -316,7 +316,7 @@ constexpr std::array<GekkoOPTemplate, 15> table63{{ {12, &JitArm64::frspx}, // frspx {64, &JitArm64::mcrfs}, // mcrfs - {583, &JitArm64::FallBackToInterpreter}, // mffsx + {583, &JitArm64::mffsx}, // mffsx {70, &JitArm64::FallBackToInterpreter}, // mtfsb0x {38, &JitArm64::FallBackToInterpreter}, // mtfsb1x {134, &JitArm64::FallBackToInterpreter}, // mtfsfix |